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|Position Title : Logic Design Engineer|
|Department : PSG Engineering|
|Position Type : Full Time|
|Location : Santa Clara, CA|
|Job Code : 2016-3188|| |
The Teledyne LeCroy Protocol Solutions Group ("PSG"), with its headquarters in Santa Clara, California, specializes in highly sophisticated development tools for high speed, serial data protocols. Teledyne LeCroy protocol analyzers and exercisers are in the critical design and test path for the vast majority of the world's leading semiconductor, device and system companies. Designers and engineers use our tools to generate and monitor traffic over the latest high-speed serial data interfaces, including USB, PCI Express, Serial ATA, Serial Attached SCSI, Fibre Channel, Ethernet, DDR and M-Phy
We are looking for a Logic Design Engineer with the right composition of knowledge, experience, spirit and drive, to join a dynamic team that develops leading edge test and measurement products. Engineering teams around the globe use our systems to develop next-generation communication, consumer electronics and computer products
Design and test FPGA circuitry for next generation Test and Measurement Tools:
Work with customer support to reproduce and fix issues found in the field
- Define logic architecture of various blocks of the design
- Design these blocks using Verilog and verify their block level functionality through simulation
- Document the design and review with the rest of the team
- Drive FPGA tools to compile the code and ensure timing closure
- Verify proper operation of your circuit via system level test with test hardware
- Work with the verification engineer to validate your circuit in a whole chip simulation environment
- Reproduce customer environment to reproduce any failures found in the field
- Fix the RTL, recompile the FPGA and review the changes
- Strong interpersonal, organizational and communication skills – a must!
- Team Player, Persuasive, encouraging, and motivating
- Open minded, quick learner, creative, likes challenges
- Experience at working both independently and in a team-oriented, collaborative environment is essential.
- Minimum of 5 years of demonstrated experience in FPGA or ASIC design
- Ability to effectively prioritize and execute tasks in a high-pressure environment.
- Knowledge of FPGA tools such as Quartus, Vivado, Modelsim, Signal tap, and Chipscope.
- Ability to write timing contraints and designs that repeatedly achieve timing closur
- Experience with Monitoring and/or Test & Measurement tools
- Experience with one or more of the following protocols: PCIe, USB, SAS, SATA, Infiniband
- BS in EE, CS or Computer Engineering – a must
- MS in EE is a plus
Teledyne is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex including sexual orientation, gender identity and pregnancy, national origin, age, disability, or protected Veteran status, or any other characteristic protected by applicable federal, state, or local law. To see our Policy on EEO click here. You may also view the EEO is the Law Poster by clicking here and its supplement.
In compliance with the ADA Amendments Act (ADAAA), if you have a disability and would like to request an accommodation in order to apply for this position with Teledyne LeCroy, please email email@example.com or call (845) 425-2000 and ask to speak with Human Resources. Determination on requests for reasonable accommodation will be made on a case-by-case basis. Please note that only those inquiries concerning a request for reasonable accommodation will receive a response.
Teledyne LeCroy is a participant in E-Verify (English | Spanish) and Pay Transparency. Details on Right To Work may be found in English and Spanish.