The time domain gating algorithm on LeCroy SPARQ Signal Integrity Network Analyzers de-embeds fixtures and launches without requiring any special calibration such as TRL or OSLT in order to set a reference plane to a point other than the default. To perform gating, users need to provide electrical delay (ns) and loss characteristic (db/GHz/ns). This operating note describes how to determine the delay and loss values.
Determining Loss and Delay using 1x or 2x Reference Structures
The most accurate measurements for delay and loss are obtained by using a reference trace such as a “1x”, “2x” length that is specifically designed for the purpose of characterizing the properties of traces to be de-embedded via gating or other calibration. “X” represents the electrical length of the trace in the fixture to be de-embedded. When designing test fixtures, include a test coupon or section of the fixture that include these reference structures.
Procedure to Obtain Initial and Refined Measurements for Delay
- Measure the S-parameters of the reference structure, and configure S1 and S2 to display S21 step and phase plots.
- Apply the horizontal cursor to the S21 step response to get an initial estimate of the electrical delay. Zooming the trace facilitate making the measurement. Read the time (X1 position) from the lower-left corner of the display. (e.g. 420 ps).
- Refine this result by finding the value of delay, that, when applying gating to the reference trace measurements, gives as close to a horizontal line as possible for the phase plot. In the screenshot below, the gating is setup to gate out the reference structure by putting ½ of the delay on each port. This creates a zero-length structure. A value of 217 ps provides the best result. If the reference structure measured is a “2x” length, then 217 ps would be the best measurement of the 1x length, and is the delay to use when applying time domain gating to the DUT. Twice this number, 434ps, is the delay of the 2x reference trace.
Procedure to Obtain Initial and Refined Measurements for Loss
- Configure S1 to show the insertion loss (dB result)
- Use horizontal relative cursors to make an estimate of the slope of the S21 trace. In the Cursor Setup dialog, set the cursor mode to show slope. Read the slope from the descriptor box for the trace: 157pdB/Hz. Multiply by 10^9 to convert to dB/GHz (0.157 dB/GHz).
- Divide by the value determined for the delay in nanoseconds (e.g. 0.434ns) to get the initial estimate of the loss characteristic: 0.362 dB/GHz/ns. (Make sure to use the electrical length of the reference trace, and not half the value.)
- Refine this result by finding the value of loss that, when applying gating to the reference trace measurement, gives as close to a horizontal line as possible for the insertion loss. In the screenshot below, the gating is setup to gate out the reference structure by putting ½ of the delay on each port. This creates a zero-length structure. When all the loss has been attributed to the “gated elements”, the insertion loss will be as close to 0 dB as possible. 370 mdB/GHz/ns is a suitable result.
Applying Your Settings
Now that results for delay and loss have been determined, they can be used for gating the fixture.
- . Add your values for Delay and Loss into the user interface as show in the image above.
- Enable the checkboxes as show in the image above to enable the gating feature globally and for all ports in use, and to use the Peeling algorithm.
- Click “Recalculate” at the top of the application to apply the gating. Subsequent measurements will use the gating setup.
Determining Delay and Loss When a Reference Trace is Unavailable
When a 1x, 2x or other reference structure is unavailable, delay and loss are more difficult to determine. The delay can be approximated by making a cursor measurement on the impedance profile of the DUT itself. In the screenshot below, we are estimating that the interface between the fixture and the DUT is at the cursor position, (180.5 ps)
To estimate loss use the S11 measurement of the fixture without a DUT connected. Since the far end is open, the S11 will begin at 0 dB, but will not be mostly linear like the S21 plot in the procedure show above. Use cursors to estimate a slope, and divide the estimate by two since it represents double the length of the gated element.
Note that the Gating dialog includes checkboxes to enable “Peeling”. When checked, the gating algorithm will use the measured impedance profile to peel out the effects of multiple reflections. With Peeling unchecked, the algorithm uses the value entered in the “Z” column. This technique is called “Port Extension” on other instruments. Leave peeling checked for best results.