ESD (electrostatic discharge) is a natural phenomenon with which most people are familiar: wherein the simple act of traversing a carpeted floor in stocking feet and flipping a light switch, or closing a car door after sliding out from behind the wheel, results in a little stinging, snapping arc. While merely a minor annoyance to us, ESD is a significant threat to electronic devices.
Automotive electronic components are designed to have, and are tested to ensure, a certain level of immunity to ESD. The tests address a variety of conditions the components will encounter during packaging, handling, vehicle assembly/service, and intended operation. Test levels range from 2 kV to 25 kV in both polarities, and are typically performed by stepping up the applied voltages to an established limit. The component surfaces, interfaces, and electrical terminals are subjected to direct air and contact discharges while unpowered, and while configured and operating in a predetermined mode. While powered, the component may also be exposed to indirect discharges that produce a radiated disturbance. We monitor the component for deviations in operation as well as inspect it for damage or degradation of performance upon test completion. Similar procedures take place at the full vehicle level as well.
ESD Measurement Configuration
The verification of the ESD simulator includes characterizing the discharge pulse waveform. The second edition of ISO 10605 identifies rise time, first peak current, current at t1, and current at t2 as the parameters of interest (Figure 1). When it comes to verifying the time constant of a given RC network, the values of t1 and t2 vary with the value of R and C.
Figure 2 shows an ESD simulator gun applying a contact discharge into a current shunt target. The target connects to the oscilloscope’s 50Ω DC-coupled input via a double-shielded cable and in-line attenuators.
ESD Thresholds and Measurement Accuracy
Although this measurement is a standard requirement, often inaccuracy stems from two main causesthe threshold selection and the choice of vertical sensitivity. Traditional pulse measurements require an oscilloscope to determine the steady-state high and low values of the pulse, and then compute pulse parameters such as rise time based on these steady-state levels. A problem occurs when using industry-default measurement thresholds.
The red histogram in Figure 3 identifies the top and base of a waveform. For clock signals, the default thresholds automatically identify the 0% and 100% levels of a waveform, leading to correct calculation of timing measurements such as rise time for a clock waveform.
However, this method for threshold placement falls short when applied to an ESD pulse, shown in Figure 4. In the case of an ESD pulse, the standard IEEE top and base thresholds will misidentify the 100% threshold at the semi-stable portion of decay labeled as "top" in the figure. It will also misidentify the 0% threshold as the prolonged decay area labeled "base" in the figure, rather than using the Zero Volt and Maximum ESD pulse values required in standards such as the IEC 61000-4-2 and ISO 10605:2008 specifications. Because standards such as these require placement of the 100% threshold at the Maximum level of the waveform, and placement of the 0% threshold at the Zero Volts level, default threshold placement will result in an erroneous rise time calculation of an ESD pulse.
The prolonged decay area of the pulse, highlighted with a dashed red line in Figure 5, will by definition, be misinterpreted by every oscilloscope as being the 100% steady state Top level of the waveform (and the peak of the waveform misidentified as being overshoot). Use of default thresholds causes incorrect determination of the rise times. Considering the vertical distance between the dashed red line and the solid green line in Figure 5, is it easy to envision how the rise time could be miscalculated with an error margin between 100% and 800%, relative to EMC standard specification requirements. One can prevent this measurement error by reconfiguring the two automatic 0% and 100% thresholds to the Zero Volt level and the waveform Maximum level respectively (circled in green in Figure 5).
Vertical Scaling and Dynamic Range
The second most common source of inaccuracy in ESD pulse measurements is the user selection of Volts per division. As shown in Figure 6, after analog amplification, the analog input signal (in this case, an ESD pulse) is fed to the analog-to-digital converter (ADC). The range of signal amplitudes that the ADC can process effectively determines the dynamic range of the oscilloscope. That range’s minimum occurs where signal power equals noise power. Its maximum occurs at or near full scale, using maximum counts of the ADC while digitizing the waveform with minimal distortion.
If we acquire an ESD pulse while it occupies only half of the vertical scale of the screen, then the acquired waveform will lose one bit of resolution (and half of its dynamic range), impacting both vertical and horizontal measurements on the waveform. Horizontal measurements are directly impacted by timing uncertainty from spurious noise at measurement points.
Many oscilloscope users are not aware that for all available digitizing oscilloscopes, the vertical resolution of an acquired waveform on the display screen is proportional to the percentage of the screen vertically occupied by the waveform.
Figure 7 shows a full-scale acquisition of an ESD pulse; note that the pulse vertically occupies the entire grid. Such acquisitions minimize quantization noise. Because quantization noise of an acquired waveform impacts both vertical measurement accuracy as well as horizontal measurement accuracy (therefore affecting measurements such as rise time), the scaling of an acquired ESD pulse is essential.
Figure 8 shows the same ESD pulse acquired while occupying only half of the grid's vertical space. A typical benchtop oscilloscope in an EMC lab contains 8-bit ADC hardware, which has 28 = 256 vertical quantization levels. When using only half of the vertical range of the display grid, only half of the ADC range comes into use when the signal is supplied from the analog amplifier output stage (referring again to Figure 5). The other half of the ADC range acquires nothing. Using only 128 of the ADC’s quantization levels yields 128 = 27 = 7-bit resolution on the acquired ESD pulse.
Figure 9 shows the same ESD pulse acquired while occupying only one quarter of the display grid, resulting in only 25% of the oscilloscope’s dynamic range being applied to the signal. In this case, only a maximum of 64 of the 256 quantization levels are used for acquiring the ESD pulse, or 64 = 26 = 6-bit resolution on the acquired ESD pulse. The loss of vertical resolution results in increased quantization noise, which impacts vertical as well as timing measurements. This can severely impact ESD pulse rise time measurementssimply based on the operator's selection of the V/div setting used during acquisition.
For this reason, vertical scaling of any digitizing oscilloscope should be set to maximize the ESD pulse shape vertically within the display grid as shown in Figure 7. This often-overlooked step has a profound impact on signal integrity and ESD pulse measurement results.
Note that for RC networks where R = 2 kOhms, the ratio of the first peak current to the current at t2 is 25:1. This is the largest ratio of measured amplitudes in a single waveform capture during verification and provides a great case for taking full advantage of an oscilloscope's dynamic range.
In summary, two of the most common pitfalls in ESD pulse measurement can be avoided when the oscilloscope operator becomes aware of them. The default threshold measurements of Top and Base must be changed to 0V – Max in order to avoid incorrect automatic threshold placement, and the vertical scaling of the ESD pulse used during verification should fill most of the grid vertically in order to maximize dynamic range and signal integrity.