The new Kibra 380 DDR3 Analyzer features DIMM slot interposers to monitor and record data traffic between the motherboard and the DDR3 U/RDIMMs. This Technical Brief discusses the design of these interposers for capturing traffic on a Kibra 380 Analyzer.

The key features of the Kibra 380 System include:

  • High Speed DDR3 Protocol Validation
  • Captures Clock, Address, Command and Control Lines
  • Passive 240-pin DIMM Slot Interposer
  • Supports speeds up to DDR3-1600
  • Supports JEDEC PC3-12800, PC3-10600, PC3 8500 and PC3-6400 DDR3 modules

Figure 1:

Kibra System Overview


The Kibra interposer uses an extender design and does not require a dedicated DIMM slot. It provides quick and easy connection between the DIMM slot and the DIMM under test. Each Kibra protocol analyzer monitors a single memory channel and can support up to two DIMM slots per channel via the DIMM slot interposers. The Kibra analyzer supplies power to the interposers via the Slot One interposer. The interposers get power from the analyzer rather than take power from the DIMM slot. This allows the components on the interposer to be powered on and available to capture traffic during the boot process.

NoteWith the first hardware release, the lock time of the registers to the clock signal prevents the Kibra from capturing the initialization of the DIMMs. This lock time is currently 3-6 microseconds. This will be improved in the second hardware release.

Figure 2:

Kibra Slot One Interposer

The slot two interposer has a slightly different layout, with only one cable from the interposer to the Kibra. This is to reduce loading on the second slot by only tapping the unique signals passed to Slot 2. All common signals between Slot 1 and Slot 2 are tapped via the slot 1 interposer.

Figure 3:

Kibra Slot Two Interposer

All DDR3 signals to the DIMM are passed straight through the interposers. The one inch of Interposer length adds ~90 picoseconds of latency to these signals.

Each Kibra slot interposer uses tapping resistors to capture the Clock, Address, Command and Control lines. The resistors passively tap the signal lines and feed the signals into two registers. The high impedance inputs of the registers along with the tapping resistors create a high impedance probe. The tapping resistors isolate the DDR link from the stub created from the registers to the Kibra. The registors sample the signal at the tapping resistor and regenerate the signal to the Kibra analyzer. The Vref signal supplied by the DIMM slot is also input to the registor. The Vref signal is then used by the register to determine valid signals during sampling.

This close proximity of the registers to the tapping point, results in a much cleaner signal eye (less signal loss, less reflection) at the register. The registers then re-drive this signal to the analyzer.

Figure 4:

Passive Tapping of Signal Lines in Kibra System

The Kibra implementation differs from that used by standard logic analyzers. Typical DDR interposers for logic analyzers use tapping resistors on all lines, which are then fed into the front end of the logic analyzer. The signal is then sampled by the front end where it must deal with signal loss as well as the reflection on the probe cables. Now that the signal is sampled, the logic analyzer user must program the desired Vref as well as the “Setup” and “Hold” time for proper sampling of the signal eye. This signal “calibration” must be done for all signals being captured. Calibration of the data lines represents an added burden for logic analyzers as data is clocked on both the rising and falling edge of the differential signaling.

Figure 5:

Tapping Resistor Design used by Typical Logic Analyzer