The Complex nature of DDR3 signaling has long been a problem for engineers attempting to validate and debug DDR3 implementations. The traditional approach for debug is the use a general purpose logic analyzer with dedicated probes or interposers to tap the necessary signals.
Signal Calibration with a Logic Analyzer has become a significant hurdle for engineers involved in system level verification. It requires that the engineer spend long periods of time setting up the logic analyzer to capture a clean and valid signal. Users must manually calculate the appropriate Vref as well as the “Setup” and “Hold” time for proper sampling of the signal eye. This signal “calibration” must be done for all signals being captured. Calibration of the data lines represents an added burden for logic analyzers as data is clocked on both the rising and falling edge of the differential signaling.
A New Approach
LeCroy has developed a new low-cost approach to System Level debug of DDR3 memory systems. The LeCroy Kibra™ 380 is a stand-alone DDR3 protocol analyzer that provides DDR3 bus and JEDEC timing analysis with the goal of fast setup and short learning curve.
This new system relies on a passive probing method which eliminates the need for calibration and training of test equipment. With LeCroy’s Kibra 380 DDR3 system, signal sampling is done directly on the Interposer rather than at the analyzer. This close proximity to the actual DDR signals allows for capture of a cleaner signal eye without calibration.
Implementation
The Kibra interposer uses an extender design and does not require a dedicated DIMM slot. It provides quick and easy connection between the DIMM slot and the DIMM module under test. Each Kibra protocol analyzer monitors a single memory channel and can support up to two DIMM slots per channel via the DIMM slot interposers. The Kibra analyzer supplies power to the interposers via the Slot One interposer. The interposers are powered from a power connection on the analyzer rather than take power from the DIMM slot. This allows the
components on the interposer to be powered on and available to capture traffic during the boot process.
The slot 2 interposer has a slightly different layout, with only one cable from the interposer to the LeCroy DDR3 analyzer. This is to reduce loading on the second slot by only tapping the unique signals passed to Slot 2. All common signals between Slot 1 and Slot 2 are tapped via the slot 1 interposer.
All DDR3 signals to the DIMM are passed straight through the interposers. The one inch of Interposer length adds ~90 picoseconds of latency to the signals.
Each Kibra slot interposer uses tapping resistors to capture the Clock, Address, Command and Control lines. By focusing on state-based capture and excluding the data signals, the system provides full visibility to JEDEC ordering violations allowing fast debug of DDR3 memory controllers. The resistors passively tap the signal lines and feed the signals into two registers. The high impedance inputs of the registers along with the tapping resistors create a high impedance probe. The tapping resistors isolate the DDR link from the stub created from the registers to the analyzer. The registers sample the signal at the tapping resistor and regenerate the signal to the Kibra system. The Vref signal supplied by the DIMM slot is also input to the register. Vref is used by the register to determine valid signals during sampling. This close proximity of the registers to the tapping point, results in a much cleaner signal eye (less signal loss, less reflection) at the register.
Logic Analyzer Probing Issues
The Kibra implementation differs from that used by standard logic analyzers. Typical DDR interposers for logic analyzers use tapping resistors on all lines, which are then fed into the front end of the logic analyzer. The signal is then sampled by the front end where it must deal with signal loss as well as the reflection on the probe cables. Now that the signal is sampled, the logic analyzer user must program the desired Vref as well as the “Setup” and “Hold” time for proper sampling of the signal eye. This signal “calibration” must be done for all signals being captured. Calibration of the data lines represents an added burden for logic analyzers as data is clocked on both the rising and falling edge of the differential signaling.
