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1881M FAST CONVERTING, 13-BIT
CHARGE ANALOG-TO-DIGITAL CONVERTER
- High Density, 64 Channels Per FASTBUS Slot
- Short Conversion Time, 12 µsec in 13-Bit Mode (9 µsec in 12-Bit
- Full 13-Bit Resolution Above Pedestal
- High Sensitivity, 50 fC/count
- Sparse Data Readout
- Multiple Event Buffer, 64 Events
FOR HEAVY ION AND PARTICLE PHYSICS CALORIMETERS
The FASTBUS Model 1881M contains 64 channels of analog-to-digital converter
(ADC) with current integrating inputs, and 13-bit resolution. These gated
integrating ADCs can be used to encode photomultiplier and chamber signals
or to sample slowly varying signals. DC-coupled gated integrators are best
suited to high rate applica tions, especially when a wide dynamic range
The 1881M has been designed for short conversion time, maximum data throughput
and short dead time, as required in state-of-the-art physics experiments.
Data can be compacted (zero suppressed) through on-board circuitry to reduce
data volume and transfer time. The 1881M contains a multiple event buffer
which can store up to 64 events. This buffer can be read out at up to 10
megawords/sec, substantially reducing the dead time of the data acquisition
The 64 inputs are accepted via standard double row headers often used with
mass terminated cables.
1881M Block Diagram
The 1881M ADC circuit is based on two LeCroy custom monolithics, an MQT200S
charge-to-time converter followed by an MTD133B time-to-digital converter,
using the linear Wilkinson run-down technique.
The MQT200S and an external capacitor form a integrator circuit which is
active during the gate period. At the termination of the gate the integrated
charge is removed from the capacitor by a constant current source within
the MQT200S producing an output pulse, the duration of which is proportional
to the input charge. This time duration is measured by the MTD133B. The
high resolution of the MTD133B permits the accurate conversion of a wide
range of values. The 1881M guarantees a linear range of 8192 codes above
the pedestal in 13-bit mode (see Figure 1) with typically ±7% differential
non-linearities (see Figure 2). Data translation and transfer times of the
MTD133B produce a total conversion time of 12 µsec.
Sparse Data Readout
Sparse data readout is a scheme which can be used to remove unwanted data
from the module, for example, the background digitized when no pulse arrives
on a channel during the gate. The 1881M allows the user to specify a set
of 64 constants (one for each channel) which can be compared to the measurements.
Only data exceeding these individual thresholds is included in the event
data buffer. The sparse data readout feature can dramatically reduce the
quantity of data which must be transferred over FASTBUS to the computer
for processing (see Figure 3).
Multiple Event Buffering
The module contains a 64-event buffer. This digital memory buffer provides
two primary advantages. First, dead time in the experiment is reduced because
data readout can be done while waiting for the acquisition of subse quent
events. Secondly, the event data can be stored temporarily while the trigger
decision to read or discard the event is made. Events in the 1881M buffer
are discarded with a FASTBUS command to skip the event. This skip command
causes an internal pointer to increment, positioning the next event at the
top of the readout queue. As each event is recorded a modulo 64 event tag
number is appended to it, in order to allow the coherence across multiple
modules to be verified.
Readout During Conversion
The module supports readout during conversion of earlier events from the
buffer with no penalty in conversion time or FASTBUS performance. There
is a slight increase in ADC noise. When readout is done during conver sion,
a typical performance is 1.2 counts R.M.S.
Control and Readout
The 1881M may be used with the optional Model 1810 Calibration and Trigger
(CAT) to provide the Calibration and Trigger signals required by the ADC.
Operation without a CAT is also possible using the front-panel Gate and
Fast Clear Inputs. However, gate and clear fan-outs and the calibration
voltage must then be supplied by the user. All modules are in accordance
with the FASTBUS Standard (ANSI/IEEE-960).
The modules may be read out via a LeCroy Model 1821 FASTBUS Segment Manager/Interface
(SM/I). The Model 1881M is compatible with the LIFT (LeCroy Interactive
FASTBUS Toolkit) software package.
The 1881M contains self test circuits allowing the operation of all ADC
channels to be verified. The self test circuits are voltage-programmed pulse
generators. A DC level (TEST REF) is bused from the 1810 CAT module to all
modules within the FASTBUS crate using the FASTBUS UR lines. When the module
is gated via CSR 0, the leading edge of the Gate causes a well defined charge
(proportional to the TEST REF Level) to be deposited in each of the inputs.
GENERAL (Specifications refer to 13-bit mode)
ADC Type: Gated current integrating Wilkinson, software operable
12/13 bit resolution.
Signal Inputs: 64 input channels. Single-ended fixed or floating
ground nominally 100 ohm; can be configured as 50 ohm. Inputs are diode
Signal Input Connector: Four 34-pin front-panel headers.
Gate Input: Differential ECL input either front-panel, or FASTBUS
TR1 and TR2, 50 - 500 nsec.
Common Mode Rejection Ratio: > 50 dB for ±200 mV DC to 1
Conversion In Progress (CIP) Output: Front-panel differential ECL,
indicating that the unit is not yet ready for another gate input.
Fast Clear: If a clear is given within 7 µsec of the first gate
trailing edge, then the gate can be applied 1 µsec later with typically
< 1 code shift. If the gate is applied 600 nsec after the clear then
< 3 code shift is typical, < 6 code shift guaranteed.
Pedestal: 200 - 800 counts.
Full Scale: 8192 counts above the pedestal.
Sensitivity: 50 fC/count.
Integral Linearity: ±10 counts maximum (tested with 500 nsec
Differential Non-Linearity: ±15% from 10 - 100% full scale,
±7% typical (tested over typical range of 20 adjacent codes).
Operating Region: +10 mV to -1.5 V for specified linearity, (+0.2
mA to -30 mA into 50 ohm - Sample Tested).
Noise: 0.7 count R.M.S. typical, 1.1 R.M.S. count maximum, tested
with constant conversion rate and discon nected inputs, without readout
Interchannel Isolation: 75 dB typical, 66 dB minimum.
Temperature Coefficient: ±(0.05% of reading + 1 count)/°C,
inputs unconnected or capacitively-coupled.
Long Term Stability: ±(0.25% of reading + 1 count)/week - Sample
Conversion Time: 12 µsec for all 64 channels in 13-bit mode,
9 µsec of all 64 channels in 12-bit mode.
Multiple Event Buffer: The digital data memory is logically organized
as a circular buffer, large enough to store the results of up to 64 events
when used appropriately. One buffer is always dedicated for FASTBUS readout.
Data Compaction: Only the contents of channels greater than their
programmable threshold will be stored.
Fast Clear Window: If the fast clear is guaranteed to always occur
before the end of conversion then the Fast Clear Window (FCW) can be set
equal to the conversion time. In this case there is NO conversion time penalty
for the fast clear window. If longer fast clear windows are required they
can be programmed up to 32 µsec in 2 µsec steps. In this case
the end of conversion will be extended to the end of the FCW.
Pedestal Gate Width Dependence: < 25 fC/nsec.
Self Test Feature: Needs an external DC voltage and a Gate signal
(e.g., from Model 1810 CAT); voltage range is 0 to 6 V (±20%).
Power Requirements: +15 V at 0.7 A; +5 V at 5 A; -2 V at 2 A; -5.2
V at 6 A; -15 V at 0.1 A.
Packaging: Single-width FASTBUS module (ANSI/IEEE 960-1989).
Addressing Modes: Geographic, Logical, and Broadcast (all classes).
Implemented Registers, FIFO.
Implemented Addressing Modes: Logical (16 bits), Geographical, Broadcast.
AS-AK Handshake Time: 125 nsec typical, 150 nsec maximum.
DS-DK Handshake Time: 65 nsec typical, 75 nsec maximum.
Module Identification Code: 104Fh.
Control and Status Registers
CSR 0h - Module ID and control status.
CSR 1h - FCW settings and gate and clear routing.
CSR 3h - Logical address.
CSR 5h - Word count for block transfers (automatically loaded by LOAD NEXT
EVENT command (CSR0 bit 8)).
CSR 7h - Broadcast class.
CSR 10h - Read\writeable pointers to circular buffer automatically advanced
by incoming events and LOAD NEXT EVENT command.
CSR C0000000h- Sparsification thresholds one per channel.
Slave Status Responses to Data Cycles:
0 = Valid Action
2 = End of Data
7 = Error. Invalid Secondary Address loaded into internal address register.
Implemented Broadcast Functions
Code Significance Comments
01h* - General Broadcast Select: The 1881M modules are selected and respond
to subsequent data cycles.
X5h - Class N Broadcast: The 1881M with class bit X set are selected and
respond to subsequent data cycles.
09h - Sparse Data Scan: 1881M modules containing at least one event assert
the T pin on the following read data cycle.
0Dh - All Device Scan: All 1881M modules assert their T pin on the following
read data cycle.
BDh - ADC Sparse Data Scan: Unique Sparse Data Scan for 1880 Series modules
only. Follows standard Sparse Data Scan (see above).
CDh - ADC Data Scan: Second level sparse data scan for 1881/1881M modules.
ADCs with at least one data word above threshold for the current event waiting
to be read out will assert T pin.
* An h subscript indicates hexadecimal (base 16).
Copyright© April1996. LeCroy is a registered trademark of
LeCroy Corporation. All rights reserved. Information in this publicaction
supersedes all earlier versions.