LeCroy Introduces New Class of Instrument Combining Functions of Signal Generator, BERT, Protocol Editor, and Serial Data Analysis System

Santa Clara, CA, February 2, 2009 - LeCroy Corporation, a leading supplier of oscilloscopes, protocol analyzers and serial data test solutions, today announced the launch of a new class of instrument, the PeRT3 Protocol-enabled Receiver and Transmitter Tolerance Tester. Developed through the synergy of the LeCroy electrical test and protocol test technologies, the PeRT3 test system combines the functions and features of a signal generator, bit error rate tester (BERT), protocol editor and serial data analysis system in one instrument. Addressing the space between physical layer test and protocol test, the new instrument complements the existing LeCroy oscilloscope, serial data analyzer and protocol test product lines to deliver complete characterization of emerging designs in development or automated test environments. The PeRT3 test system is designed to meet the comprehensive test needs of engineers working with serial data transceivers, high-speed serial data communication systems, and other electronic systems. PeRT3 not only measures adherence to specifications, but provides deeper insight through the examination of the entire performance envelope of the system under test. Serial data standard support includes protocol handshake, loop-back and Frame Error Rate analysis as well as receiver compliance testing for PCI Express®, SATA, SAS and USB 3.0.

Map the Full Performance Envelope along Multiple Dimensions

Beginning with a high quality, low jitter signal generation system and then measuring performance through BERT or through protocol level errors (such as CRC errors), PeRT3 has the unique ability to introduce controlled signal degradations that create specific types of modulations in varying but controlled amounts. PeRT3 modulates the signal noise, jitter, amplitude, rise/fall time, pre-emphasis/de-emphasis and other typical noise sources. Varying the type and amount of jitter and modulation introduced, while counting the errors on the returning signal, PeRT3 maps out the full performance envelope of the device under test along multiple dimensions. This provides not just a GO/NO-GO test, but quantifies the error margins and error susceptibilities of each new design or each tested device.

The PeRT3 test system includes intelligent reporting capabilities for analysis and documentation of deep statistical tests. Should failure occur during the test, the environment that caused the failure can be reproduced by zooming in on the area of interest and applying a more extensive stress profile for design engineers to troubleshoot. In addition, the PeRT3 GUI is simple and user-intuitive, taking just a few steps to get the DUT into loop-back mode ready for a test.

Protocol Enabled for Complete System Control, Real Data Traffic Generation, and Protocol Level Error Testing

Protocol enabling is a key advantage to using the PeRT3 test system. The PeRT3 test system provides system control over the test configuration enabling automated testing. For example, the system can automatically command the remote device to enter a loop-back mode while a test is in progress

The system can also generate test traffic that goes well beyond simple “pseudo random bit sequences” (PRBS) by using real data traffic. In addition, PeRT3 intelligently manages protocol-specific issues that cause disruptions, such as the resynchronization of clocks in SATA through the use of the ALIGN primitive. Finally, the system can use protocol level error testing as one means for evaluating the system performance, measuring protocol-specific errors such as CRC errors, R_ERR in SATA or ACK/NAK in PCI Express.

Serial Data Generation and Jitter Testing

The BER generator and detector function operates at up to 6 Gb/s. An integrated pattern generator generates protocol level traffic using 1 GB user memory per channel with frames and data scrambling. Automated test scripts allows for continuous testing for deep BER depth.

The PeRT3 system provides multichannel support with independent jitter profile and analysis for each channel. Jitter tolerance testing can characterize and qualify high speed serial transceivers, and is stress injection capable with complete jitter profiles including random jitter (Rj) and deterministic Jitter (Dj).

SSC Support can be enabled or disabled for silicon bring-up testing. Pre-emphasis with control of amplitude and duration is available as well as sweepable signal voltage for DUT input sensitivity test.

Further Information

Engineers and technicians who would like to know more can visit the LeCroy web site www.lecroy.com

About LeCroy

LeCroy Corporation is a worldwide leader in serial data test solutions, creating advanced instruments that drive product innovation by quickly measuring, analyzing, and verifying complex electronic signals. The Company offers high-performance oscilloscopes, serial data analyzers, and global communications protocol test solutions used by design engineers in the computer and semiconductor, data storage device, automotive and industrial, and military and aerospace markets. LeCroy’s 40-year heritage of technical innovation is the foundation for its recognized leadership in “WaveShape Analysis”—capturing, viewing, and measuring the high-speed signals that drive today's information and communications technologies. LeCroy is headquartered in Chestnut Ridge, New York. Company information is available at www.lecroy.com.