Products
Protocol Analyzers

Eclipse M32x UniPro/UFS Analyzer/Exerciser

The Eclipse M32x analyzes bi-directional UniPro and UFS traffic, performing protocol sequence and timing analysis and packet header and payload inspection, to provide complete protocol debug and analysis of UniPro and UFS devices. Trace Validation uses state machine logic to analyze captured traces algorithmically without user intervention. The Eclipse M32x also provides conformance/compliance verification, as well as margin, corner case, and automated stress testing.

Explore Eclipse M32x UniPro/UFS Analyzer/Exerciser  Explore Eclipse M32x UniPro/UFS Analyzer/Exerciser
Eclipse T42 UniPro/UFS Analyzer   is an entry level analyzer to address next tier implementations in the UFS ecosystem. The Eclipse T42 Analyzer supports MIPI M-PHY v4.1 HS-G4B, UniPro v1.8 and UFS3.0, and M-PHY v3.1 HS-G3, UniPro v1.61, and UFS2.1. Supporting HS-G4, the unit includes x2 solder down probes. The Eclipse T42 Protocol Analyzer can be upgraded to the advanced feature set of the Eclipse M42x Protocol Analzyer.
Eclipse M42x UniPro/UFS Analyzer/Exerciser  

Implementing a new high speed front end, supporting MIPI M-PHY™ Gear4 at speeds up to 11.8Gbps, the Eclipse M42x stands as the markets most complete analyzer/exerciser. The Eclipse M42x is the right tool for engineers and developers who need to ensure the correct and efficient operation of technologies employing the high data transfer speeds of the UniPro/UFS specifications.

Eclipse T32 UniPro/UFS Analyzer   based on the above Eclipse T42 UniPro/UFS hardware, is an entry level analyzer to address next tier implementations in the UFS ecosystem. Supporting up to HS-G3, the unit includes x2 solder down probes. This lower priced analyzer provides an entry point to UniPro/UFS designs with an upgrade path to HS Gear4. HS Gear4 and the Advanced feature set of the M32x analyzer can be added later.
Eclipse M32x UniPro/UFS Analyzer/Exerciser   The Eclipse M32x analyzes bi-directional UniPro and UFS traffic, performing protocol sequence and timing analysis and packet header and payload inspection, to provide complete protocol debug and analysis of UniPro and UFS devices. Trace Validation uses state machine logic to analyze captured traces algorithmically without user intervention. The Eclipse M32x also provides conformance/compliance verification, as well as margin, corner case, and automated stress testing.
Envision X84 C/D-PHY CSI-2/DSI Analyzer  is the first combination C-PHY/D-PHY analyzer in single platform. The Envision X84 supports C-PHY/D-PHY and Cameral Serial Interface (CSI-2) and Display Serial Interface (DSI/DSI-2) on a single hardware platform. Envision X84 supports C-PHY version 1.1 and D-PHY 2.1 as well as CSI-2 version 2.1 and DSI version 1.3 and DSI-2 version 1.1. The Envision X84 offers Silicon ad device designers, integrators and validation engineers a complete, robust yet flexible tool to ensure the correct and efficient operation of Camera and Display over C-PHY and D-PHY implementations.

MIPI Alliance defines several serial PHYs for use in mobile and mobile influenced environments, such as smartphone, automotive, augmented and virtual reality, as well as IoT. MIPI C-PHY and D-PHY busses are primarily used with camera and display implementations, while M-PHY is used with storage applications. MIPI Alliance also defines multiple interfaces and transport layers such as Camera Serial Interface (CSI-2), Display Serial Interface (DSI and DSI-2); and UniPro as a transport layer for M-PHY.

The MIPI C-PHY and D-PHY busses are both used in camera and display implementations. Each bus has a different use case to allow design engineers flexibility regarding performance, power and cost. Both PHYs can be applied for many use cases, such as smartphones, automotive camera sensing systems, collision avoidance radars, in-car infotainment and dashboard displays.

MIPI C-PHYSM provides high throughput performance over bandwidth-limited channels to connect displays and cameras to an application processor. C-PHY enables designers to scale their implementations to support a wide range of high resolution image sensors and displays while keeping power consumption low. It can also be used to connect low-cost, low-resolution image sensors, sensors offering up to 60 megapixels, as well as display panels offering 4K and higher resolution.

C-PHY is an embedded clock link that provides extreme flexibility and low latency transitions between high speed and low power modes. To do this, C-PHY introduces three-phase symbol encoding to transmit data symbols on three-wire lanes, or “trios”, where each trio includes an embedded clock.

MIPI D-PHYSM also connects cameras and high-resolution displays to an application processor. Rather than using an embedded clock, it uses a clock-forwarded synchronous link that provides high noise immunity and high jitter tolerance. MIPI D-PHY also offers low latency transitions between high speed and low power modes. D-PHY is a flexible, high-speed, low-power and low-cost solution.

MIPI CSI-2SM is the most widely used camera interface in the mobile industry. Designers find using MIPI CSI-2 for any single- or multi-camera implementation in mobile or mobile influenced devices, easy to implement and supports a broad range of high-performance applications, including 1080p, 4K, 8K and beyond video, and high-resolution photography. The interface can also be used to interconnect cameras in head-mounted virtual reality devices; automotive smart-car applications for infotainment, safety, or gesture-based controls; camera drones; IoT appliances; wearables; and 3D facial recognition security or surveillance systems.

MIPI DSI-2SM, supports ultra-high definition (4K and 8k) required by new and future mobile displays. It specifies the physical link between the chip and display in devices such as smartphones, tablets, AR/VR headsets and connected cars. Designers can use MIPI DSI-2 on two different physical layers: MIPI D-PHY and MIPI C-PHY. The options give designers the flexibility to support different configurations up to four data lanes.

Although the features of MIPI DSI-2 are similar to MIPI DSI, the primary difference is its support for C-PHY. However, it also features backward compatibility with DSI on D-PHY. MIPI DSI-2 v1.1 incorporates the VESA VDC-M and VESA DSC standards in its transport layer. Companies now have the choice of either codec depending on their bandwidth and power requirements.

The M-PHY specification from the MIPI® Alliance provides flexibility and speed for developers in the mobile computing market. The technology is aimed at next generation smart phones, tablets and other low power mobile computing devices. The M-PHY currently runs at GEARs 1/2/3/4 for speeds up to 10Gbps per lane in each direction, providing asymmetrical lane operation for up to 4-lane device configurations.

MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. It is targeted to be suitable for multiple protocols and for a wide range of applications.

M-PHY uses lanes for communication. Each lane is a differential pair. M-PHY supports multiple lanes and lanes can be asynchronous.

M-PHY defines both low speed and high speed data rates. Within both low speed and high speed, multiple gears are defined. Low speed uses a Pulse Width Modulation and Gears 1-7 support a range of speeds from 3Mbps up to 576 Mbps. High Speed uses NRZ signaling and supports speeds of .998Gbps up to 11.66Gbps via Gears 1-4. Information transmitted on the lanes uses 8b/10b encoding.

UniPro is a MIPI defined transport specification. UniPro enables upper layer applications to move data over the M-PHY bus although it is Phy layer agnostic. UniPro is applicable to a wide range of Device types such as modems, storage subsystems, Non-volatile memory, displays, and camera sensors. It is also applicable to different types of data traffic such as control messages, bulk data transfer and packetized streaming. A full Layer 1.5-4 specification, UniPro defines packets and frames for moving information across a network from device to device. It also defines the structures and mechanisms for connection management, power and state management, flow control and error handling.

JEDEC defines the Universal Flash Storage (UFS) specification. UFS is a simple, high performance, mass storage device with a serial interface. It is primarily for use in mobile systems, between host processing and mass storage memory devices. The UFS electrical interface is based on the MIPI M-PHY specification which together with the MIPI UniPro specification forms the interconnect of the UFS interface. UFS is based on the SCSI Architectural Model (SAM). The UFS command set is based on the SCSI Primary Command (SPC) and SCSI Block Command (SBC) sets.

Protocol Analysis and Traffic Generation

Teledyne LeCroy offers both protocol analyzers and traffic generators or exercisers to address the above markets. The Envision product line offers the first combination C-PHY/D-PHY analyzer in a single platform. It supports CSI-2 and DSI/DSI-2 over either C-PHY or D-PHY. The Envision X84 uses a robust event-based infrastructure for capturing detailed CSI/DSI protocol information on a C/D-PHY bus. it offers flexibility to capture either camera or display traffic using this data, allowing real-time viewing of protocol events. Time correlation of both High Speed and Low Power states, including errors is also availabel. Low-level, per-lane states can be viewed and correlated with high-level protocol, to debug errors. CTS tests can be run against any captured event file. Images and video can be benchmarked against previous saved files.

Our Eclipse protocol analyzers offer unique and configurable views that allow users the ability to easily visualize the UniPro/UFS traffic. From the low level M-PHY primitives up through the UFS SCSI command sets we show activity on the bus as a complete picture of all events, and allow views to the lowest level bytes or to the highest level command transactions. Our exerciser and expert system analysis run conformance and stress test cases, then verify that the resulting protocol sequences and packets conform to the CTS. Extensive reporting and analysis tools include reports by test parameters – status, individual tests, or test rules, and within tests by packet characteristics such as packet number, byte, speed, link, etc. Summary and full reports and pass/fail reports are also provided.

As a contributing member of both MIPI and JEDEC, Teledyne LeCroy stays informed and up to date on the latest specifications and continues to update the roadmap for their MIPI related tools.

Based on the Eclipse M42x UniPro/UFS hardware, with support for Gear 3 speeds at over 5GBps, the Eclipse M32x UniPro/UFS Analyzer is the right tool for engineers and developers who need to ensure the correct and efficient operation of technologies employing the high data transfer speeds of the UniPro/UFS specifications supported by M-PHY interfaces. Teledyne LeCroy's UniPro M Series Protocol Suite provides all the views you need to debug captured data. The Events window shows activity on the bus as a complete picture of all events and allows drill-down to the lowest level bytes. This unique time-aligned display includes fillers, Prepare, SYNC, Hibern8, sleep, stall and other M-PHY level packets. Add in the Trace Validation Expert system analysis, the Eclipse M32x delivers protocol analysis, compliance conformance verification, and automated quality testing in one powerful package.

The Advanced analysis features of the Eclipse M32x Analyzer/Exerciser includes:

  • Upgradability to Exerciser capability
  • Trace Validation feature and Trace Builder scripting
  • Advanced Triggering
  • Pre-Capture Hardware filtering
  • Optional solder probe for superior probing in demanding test environments with less than optimal signal integrity
  • Complete debug and analysis solution with combined stimulus and Trace Validation expert system analysis.
  • CTS Test Case execution
  • Stress, Margin and corner case testing
  • Custom, user-defined test case creation with Stimulus Builder scripting

The Eclipse M32x Exerciser can be configured to initiate conformance test cases or Users can also create their own test cases for fully automated testing. Trace Validation powers several of the Eclipse M32x's most exciting features. Trace Validation uses state machine logic to analyze captured traces algorithmically without user intervention. It identifies transactions on the link by analyzing millions of packets in a trace capture, then evaluates the complete protocol sequences and individual packets for conformance to the specification. Trace Validation finds the problems an engineer can't.

The Eclipse M32x Exerciser can be configured to initiate conformance test cases, then use Trace Validation to verify that the resulting protocol sequences and packets conform to the CTS. Extensive reporting and analysis tools include reports by test parameters – status, individual tests, or test rules, and within tests by packet characteristics such as packet number, byte, speed, link, etc. Summary and full reports and pass/fail reports are also provided. Exerciser stress testing controls the DUT and executes hundreds of thousands of tests automatically. Stop after any number of loops, or "No Result" test cases, and analyze the results with Trace Validation. Users can also create their own test cases for fully automated testing.