Kibra 480 Analyzer
The Kibra 480 is a stand-alone protocol analyzer that provides comprehensive bus and JEDEC timing analysis for DDR3 and DDR4. Sitting in-line on a live system, the analyzer uses a proprietary probe implementation to allow loss-less capture of high speed DDR transactions while automatically identifying timing and protocol violations.
DDR Debug Toolkit
The DDR Debug Toolkit provides test, debug and analysis tools for the entire DDR design cycle. The unique DDR analysis capabilities provide automatic Read and Write burst separation, bursted data jitter analysis and DDR-specific measurement parameters.
DDR4 is an evolutionary upgrade from DDR3. It introduces data transfer rates which are nearly double the DDR3 transfer rates, ranging from 1.6 GT/s up to 3.2 GT/s. DDR4's higher transfer rates and lower operating voltage have driven new test methodologies and test requirements which were not previously required for DDR3 in order to ensure proper signal fidelity. QPHY-DDR4 has a full suite of Clock, Electrical, and Timing tests as specified by the JEDEC Specification which will aid in DDR4 design validation.