DDR Debug Toolkit The DDR Debug Toolkit is designed to accelerate DDR design work in the early turn-on, validation and pre-compliance stages as users prepare for compliance testing. Integrated into the MAUI scope app, users can build out case by case scenarios with multiple analysis areas, perform decode and triggering on the Command Bus and dive into optimizing design stages with JEDEC specific eye diagrams, mask testing and DDR specific measurements.
QPHY-DDR3 Teledyne LeCroy QPHY-DDR3 automated compliance software enables engineers to consistently run test on DDR3/3L and LPDDR3 memory standards set by the JEDEC Specification. This includes pass/fail reporting for Electrical and Timing test requirements for Clock (CK), Strobe (DQS), Data (DQ) and the command address bus signals. Paired with the DDR Debug Toolkit provides the tools to confidently test all stages of memory design, from initial turn-on through final compliance test.