App Note: CATC's Mid-Bus Probe Solution for PCI Express

Introduction

A mid-bus probe is one of the tools that can greatly help engineers debugging PCI Express buses. A PCI Express mid-bus probing solution provides direct probing capability of a PCI Express bus at a width of up to 16 lanes. To accommodate a mid-bus probe, the standardized mid-bus probe footprint is required to be designed into the target board.

Although not part of the PCI Express specifications, the industry has developed a common mid-bus probe footprint as given in Figure 1. This footprint is recommended for use with all types of test equipment including protocol analyzers, logic analyzers and oscilloscopes.

This white paper presents CATC’s mid-bus probing solution, covering issues of mechanical constraints, electrical performance and link measurement configurations, as well as the relevant footprint and pinout requirements. System designers may use the information to incorporate the mid-bus probing solution into their design.

CATC Mid-Bus Probe Overview

The CATC mid-bus probe is a 16-channel differential signal probe that meets the demand for high-density signal access, accuracy and repeatability while providing connector less attachment to the device under test. It supports the data link configuration that is recommended in the Intel PCI Express Mid-bus Probing Footprint and Pinout Revision 1.0 document dated 8/05/03.

For the purposes of this document, “channel” refers to either an upstream differential pair OR downstream differential pair for a given lane. A corollary statement is that “channel” refers to either a Transmit differential pair OR Receive differential pair for a given lane. Flexibility is given to the platform designer to configure a probing solution that best meets the needs of the system. Specifically, the CATC mid-bus probe supports the following configurations:

• Upstream and downstream channels of one x8 link (initial release)
• Upstream and downstream channels of up to two x4, x2 or x1 links (initial release)
• Upstream or downstream channels of up to two x8, x4, x2 or x1 links (future release)
• Other combinations may be available (special handling)

CATC PCI Express protocol analyzers require a reference clock for mid-bus analysis. Each mid-bus probe is equipped with one clock probe. The CATC mid-bus reference clock probe is designed to facilitate capturing clock signals from the system board in the two configurations recommended by the Intel guideline, i.e. a tap off of an existing clock and alternately, a dedicated clock.

Mechanical Design

Mid-Bus Probe Footprint

The CATC mid-bus probe is fully compatible with the standardized mid-bus footprint recommended by the Intel guideline, as shown in Figure 1.

Figure 1:

PCI Express mid-bus footprint dimension and pin numbering.

Mid-Bus Probing Configuration

The configuration of the CATC mid-bus probe in the system under analysis is shown in Figure 2.

To prepare a circuit board for PCI Express mid-bus probing, the mid-bus footprint has to be laid out onto the target system board and a retention module has to be attached to the board. Retention module attachment is simple and quick. There are four through-hole pins and one protrusion key underneath the retention module. Align the key of the retention module with the keying/alignment hole (Figure 1) in the mid-bus footprint on the target system board, and solder the through-hole pins to the matching plated through holes located on each corner of the mid-bus footprint. The mid-bus probe can then be attached to the target system board through the retention module to provide mechanical support for pin-to-pin alignment. The mid-bus probe has 2 retention screws that connect to the retention module to hold the probe in place.

The retention module should not be confused with a PCB connector because it is not part of the electrical circuits of either the target system or the probe. With the use of a retention module, the requirement to have a keepout area on the back-side of the board is eliminated.

CATC recommends the following retention module:

Part number - P/N 600-0117-00

Manufactured by:

Precision Interconnect
10025 SW Freeman Court
Wilsonville, Oregon, USA 97070-9289
Phone: 1-503-685-9300
Fax: 1-503-685-9305
http://www.precisionint.com/

The bus signals captured by the mid-bus probe are connected via a SkewClear cable (Amphenol) to a mid-bus probe pod for amplification. The amplified bus signals are then connected to the CATC PETracer ML protocol analyzer for decoding and protocol analysis.

Figure 2:

CATC mid-bus probing configuration.

Keepout Volume

The CATC mid-bus probe requires a much smaller keepout volume than the generic keepout volume recommended by the Intel guideline. This feature allows the application of the CATC mid-bus probe in a tight space such as between add-in cards. Figure 3 shows the required keepout volume of the CATC mid-bus probe.

Figure 3:

CATC mid-bus probe required keepout volume. (Unit in inches. Not to scale)

Reference Clock Probe Attachment

The required reference clock to the analyzer is captured via a 3-pin header (1 by 3, 0.05” center spacing) on the clock signal transmission line.

If the reference clock is sampled by tapping off an existing clock, the header shall be located on the existing clock transmission line, where a high impedance clock probe from the mid-bus probe is connected with no significant loading effects. In the case of a dedicated clock, the header shall be located at the end of a dedicated clock transmission line without termination, where a 50-Ohm cable is connected and the termination for the clock signal is provided on the mid-bus probe board.

The connectivity of the clock header pins follows the recommendation of the Intel guideline as given in the following table,

Note that the analyzer is not sensitive to the polarity of the reference clock. Therefore, the probe can be plugged onto the pin header in either orientation.

The following 3-pin headers recommended by the guideline can be used for the reference clock through-hole: Samtec* TMS-103-02-S-S, or surface mount: Samtec* FTR-103-02-S-S.

Reference Clock Probe Keepout Volume

The reference clock probe keepout volume is adopted from the recommendation from the Intel guideline, PCI Express Mid-bus Probing Footprint and Pinout (8/05/03) Revision 1.0.

Electrical Design

Probe Loading Effect

The logical probing of the PCI Express bus is achieved by tapping a small amount of energy from the probed signals and channeling this energy to the analyzer. In order to avoid excessive loading conditions, the CATC mid-bus probe employs high impedance tip resistors, or isolation resistors. The probe isolation resistance is selected to both satisfy the probe sensitivity and system parasitic load requirements.

With this unique design, the CATC mid-bus probe can capture bus traffic signals with amplitudes specified by the PCI Express standard, while introducing only the loss and added jitter that are within the recommended specification in the PCI Express Mid-bus Probing Footprint and Pinout (8/05/03) Revision 1.0.

Extensive care has been constantly made to reduce the parasitic effect on the probed signals during each phase of the CATC mid-bus probe design. For detailed information on electrical characteristics of loaded signals with the presence of the mid-bus probe, please contact CATC headquarters in Santa Clara, California.

Reference Clock Output Port

The reference clock is captured separately with a dedicated probe cable. Considering the possibility that one clock may be shared between two physically separated mid-bus probes, each mid-bus probe board is equipped with a reference clock output port. The reference clock probe can not only capture signals from the target system but also receive a duplicated reference clock from another mid-bus probe board.

Mid-Bus Probe Pin Assignments

Cross-references from the PCI Express Mid-bus Probing Footprint and Pinout (8/05/03) Revision 1.0 are given in tables listed below. In the initial product release, the mid-bus probe supports only bi-directional analyzer probe pinout.

A unique feature of the CATC mid-bus probe is that the probe pinout is deliberately grouped into four quadrants. Quadrant A covers Pin 1, 3,…through Pin 23. Quadrant B covers Pin 2, 4,… through Pin 24. Quadrant C covers Pin 25, 27,… through Pin 47. Quadrant D covers Pin 26, 28,… through Pin 48. With each quadrant assigned a dedicated connection to an individual port of the analyzer, significant versatility is achieved in bus measurement configuration.

Table 1:

x8 (Bi-directional) specific PCI Express Analyzer Probe Pinout

Table 2:

x4 (Bi-directional) specific PCI Express Analyzer Probe Pinout

Table 3:

x2 (Bi-directional) specific PCI Express Analyzer Probe Pinout

Table 4:

x1 (Bi-directional) specific PCI Express Analyzer Probe Pinout

How to Contact CATC