CSR0 Bit Definitions

D0 CONV_COMP (Conversion complete) (read only).

D1 CIP (Conversion In Progress) (read only).

D2 Rear panel/front panel gate select; when a 1 is written, front panel is selected. Rear panel is the CERN Jaux Dataway, if in place.

D3 Event Buffer not full (EVENT_FULL*); when a 0 is read, the Event Count (D4 Ð D7) will be 0 indicating that 16 events have been stored in the memory.

D4 Ð D7 Event Count (0 Ð 15).

D8 Clear module; when a 1 is written, CONV_COMP and EVENT_FULL are cleared and reset. The event counter and channel counter are both reset to 0. Resets itself, always reads 0.

D9 Causes a test gate of 500 nsec to be generated when a 1 is written and then clears itself, always reads 0.

D10 Ð D15 Not Implemented.

CSR0 Bit Definitions

D0	CONV_COMP (Conversion complete) (read only).

D1	CIP (Conversion In Progress) (read only).

D2	Rear panel/front panel gate select; when a 1 is written, front panel is selected. Rear panel is the CERN Jaux Dataway, if in place.

D3	Event Buffer not full (EVENT_FULL*); when a 0 is read, the Event Count (D4 Ð D7) will be 0 indicating that 16 events have been stored in the memory.

D4 Ð D7	Event Count (0 Ð 15).

D8	Clear module; when a 1 is written, CONV_COMP and EVENT_FULL are cleared and reset. The event counter and channel counter are both reset to 0. Resets itself, always reads 0.

D9	Causes a test gate of 500 nsec to be generated when a 1 is written and then clears itself, always reads 0.

D10 Ð D15	Not Implemented.