MIQ401 4 CHANNEL CHARGE MULTIPLEXER - QMUX

 

 

LOW COST PRECISION CHARGE MULTIPLEXER FOR ADC SYSTEMS

 

The MIQ401 QMUX circuit is a 4-channel Monolithic designed to supply the integrate-and-store function required for event-based signal recording. It provides a multiplexed current source output for four charge input signals, thus allowing simple readout of many signal sources to a single ADC. The device provides two integrators per channel with sensitivity in the ratio 8 to 1 permitting a high/low encoding scheme to give a 15-bit equivalent dynamic range.

 

 

SPECIFICATIONS

 

PIN OUT SUMMARY

PIN #

NAME

DESCRIPTION

Analog Inputs 15 IN 0- Negative signal input channel 0
13 IN 1- Negative signal input channel 1
11 IN 2- Negative signal input channel 2
9 IN 3- Negative signal input channel 3
16 IN 0+ Positive signal input channel 0
14 IN 1+ Positive signal input channel 1
12 IN 2+ Positive signal input channel 2
10 IN 3+ Positive signal input channel 3
Input Control 7 Gate* Gate Input defines integration interval for the four inputs.
6 Gate Differential ECL
Analog Outputs 4 QOUT HI High-Range charge output. Channel being read out. (1/10 of integrated input charge).
21 QOUT LO Low-Range charge output. Selected by STR-lines. (8/10 of integrated input charge).
18 ISUM Fast current sum output 1/10 of input current from each channel summed together. Open collector output. 4.5<Vcoll<7 V
22 QOUTB Strobe bias
Output Control 3 CS* Chip select. Enables chip for charge output. Used for multiplexing many chips to same output bus pair.
23 STR0* Route charge from channel 0 to output buses
24 STR1* Route charge from channel 1 to output buses
1 STR2* Route charge from channel 2 to output buses
2 STR3* Route charge from channel 3 to output buses
Supply Voltages 8 V++ 12 V nominal
17 V++ 12 V clean
20 V+ 4.3 V nominal
5 GND
19 V- -3 V nominal

 

 
DC CHARACTERISTICS PARAMETER

MIN

TYP

MAX

UNIT

COMMENTS

V++ Voltage Requirement 11.5 12 12.5 V
V+ Voltage Requirement 4.2 4.3 4.4 V
V- Voltage Requirement -2.8 -3 -3.2 V
V++ Voltage Requirement ­ 10 13 mA Static condition
V+ Voltage Requirement ­ 20 25 mA Static condition
V- Voltage Requirement ­ 30 38 mA Static condition
Power Dissipation 365 mW Static condition
AC CHARACTERISTICS
Signal Inputs Input Signal Current, Neg. ­ ­ 30 mA For linear operation
Input Signal Current, Pos. ­ ­ 100 µA
Reference Signal Voltage -0.5 ­ 0.5 V
DC Input Impedance ­ ­ 0.5 Ohm For 0-30 mA
Input Offset Voltage -2 0 2 mV
Tempco of Offset Voltage ­ 5 ­ µV/°C
Input Integration Gate Gate Duration 20 ­ 2000 nsec
Gate Internal Setting Time ­ 5 10 nsec
Charge Transfer Droop Rate ­ ­ 100 fC/msec
Maximum Holding Charge 180 ­ ­ pC
Low Range (referred to input)
Maximum Holding Charge 1800 ­ ­ pC
High Range (referred to input)
Low Range Transfer Coefficient 0.75 ­ 0.8 (QoutLO/Qin)
High Range Transfer Coefficient 0.094 ­ 0.1 (QoutHI/Qin)
Low Range Charge Transfer Offset ­ ­ 20 pC
High Range Charge Transfer Offset ­ ­ 20 pC
Current Sum Transfer Coefficient 0.096 ­ 0.1 (Iisum/Iin)
Non-linearity ( Q/Qfit) ­ ­ ±(.25% + 100 fC) Referred to output
Clear Time/Readout Time ­ 500 600 nsec Within 50 fC of pedestal
Noise (rms) ­ ­ 50 fC Referred to output
Interchannel Cross Talk -60 ­ ­ dB
Temperature Coefficient <±(50 fC + 0.1% of output Q)/°C

 

Copyright© May 1997. LeCroy is a registered trademark of LeCroy Corporation. All rights reserved. Information in this publication supersedes all earlier versions. Specifications and prices subject to change without notice.