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Protocol Analyzers

Summit T3-16 Analyzer

The Summit T3-16 Protocol Analyzer captures, decodes and displays PCIe 3.0 protocol traffic.data rates for x1, x2, x4, x8, x16 lane widths

Explore Summit T3-16 Analyzer Systems Explore Summit T3-16 Analyzer Systems
Summit T54 Analyzer  The Summit T54 Protocol Analyzer captures, decodes and displays PCIe 5.0 protocol traffic data rates for x1, x2, x4 lane widths.
Summit M5x Protocol Analyzer /Jammer  

The Summit M5x is Teledyne LeCroy's PCIe/ NVMe Jammer solution and is the latest protocol analyzer targeted at high speed PCI Express 5.0 I/O-based applications such as workstation, desktop, graphics, storage, and network card applications.

Summit T416 Analyzer  The Summit T416 Protocol Analyzer captures, decodes and displays PCIe 4.0 protocol traffic data rates for x1, x2, x4, x8, x16 lane widths
Summit T48 Analyzer  The Summit T48 Protocol Analyzer captures, decodes and displays PCIe 4.0 protocol traffic data rates for x1, x2, x4, x8, lane widths
Summit T3-16 Analyzer  The Summit T3-16 Protocol Analyzer captures, decodes and displays PCIe 3.0 protocol traffic data rates for x1, x2, x4, x8, x16 lane widths
Summit T3-8 Analyzer  The Summit T3-8 Protocol Analyzer captures, decodes and displays PCIe 3.0 protocol traffic data rates for x1, x2, x4, x8 lane widths
Summit T34 Analyzer  The Summit T34 Protocol Analyzer captures, decodes and displays PCIe 3.0 protocol traffic data rates for x1, x2, x4 lane widths

The Summit T3-16 is Teledyne LeCroy's fifth generation of protocol analyzers targeted at high speed PCI Express I/O-based applications such as workstation, desktop, graphics, storage, and network card applications.

  Title Time
Summit T3-16 PCI Express Protocol Analyzer Introduction Video 4:05
Synopsys and Teledyne LeCroy Showcase PCI Express 3.0 Interoperability at PCI-SIG 2010 3:04
Demo of Synopsys DesignWare PCI Express 3.0 with Teledyne LeCroy Protocol Test Suite 4:34
IDT PCIe Switch Demo using Summit T3-16 protocol analyzer 7:15
Cadence and Teledyne LeCroy work together supporting PCI Express 3.0 development and test 1:26
PCIe 3.0 at 8.0 GT/s 3:17
Xilinx Video: Industry’s first Gen3 x 16 PCIe solution built into a programmable device 2:30
NVMe Protocol Analysis Features for Storage Development and Test 36:27

PCIe 3.0 technology achieves twice the effective data throughput rate of the PCIe 2.0 standard through a combination of increased data bit rate (5 GT/s moving to 8 GT/s) and the elimination of 8b/10b data encoding, which previously added an overhead of 20 percent to all data transfers. In eliminating 8b10b encoding, PCIe 3.0 technology now relies on the existing data scrambling techniques similar to those used for PCIe 2.0 technology to ensure that receivers maintain lock on the incoming data stream.

PCIe 3.0 speeds

With advanced features such as support for PCI Express Spec 3.0, data rates of 2.5, 5 and 8 GT/s, lane widths from x1 to x16, and a full 8 GB of trace memory, the Summit T3-16 provides unmatched capability and flexibility for developers and users of advanced PCI Express products. The Summit T3-16 is by far the most advanced and sophisticated PCI Express Analyzer available in the market today.

Powerful Views

As with other Teledyne LeCroy PCI Express analyzers, the Summit T3-16 leverages the intuitive and powerful CATC Trace analysis software system, embedding a deep understanding of the PCI Express protocol hierarchy and intricacies. The colorful, intuitive and easy to use graphical display allows you to quickly capture and validate PCI Express product designs. All Teledyne LeCroy PCI Express protocol analyzers employ high-impedance, non-intrusive probing technology, thereby allowing fully unaltered data pass-through.

Lane Swizzling

In addition to a full suite of advanced hardware and software features, the Summit T3-16 provides user-convenience and analysis features, such as support for "lane swizzling" which allows a board developer to lay out a Mid-Bus probe pad with lanes in non-standard order, simplifying the design of the board. Internally the Summit T3-16 maps the lanes back into their correct order and accurately displays the embedded bus traffic. Other software features include enhanced error checking for automatic identification of additional error types, more compact trace files that allow for faster analysis of trace data, and the choice of simplified or advanced modes for setting up trace recording options.

Bit Tracer

A new raw recording mode, Bit Tracer, allows bytes to be recorded as they come across the link, allowing debugging of PHY layer problems and combining the features of a logic analyzer format with a protocol analyzer format. The new auto sense link feature monitors negotiation between devices of different lane widths, and the bifurcated link support recombines multilink PCI Express operations that have been separated into narrower links.

Lan Support

The Summit T3-16 also supports Ethernet LAN port as a standard feature. By connecting over a LAN, engineers can operate the system remotely (e.g., install the client software on their desktop systems, and control an analyzer operating in a remote lab). Also, multiple engineers working collaboratively can time-share use of a single analyzer, reducing the need for an additional analyzer for each engineer, and increasing the cost effectiveness of the product.

Flexible Configurations

The Summit T3-16 is available in two configurations—that support either x1, x2, x4, and x8; or x1, x2, x4, x8, and x16—to match user requirements with available budgets. The upward compatibility and 13 month warranty of the Summit T3-16 also provide investment protection for current Gen1 and Gen2 users who plan to upgrade to Gen3 devices in the future.

Debug in any PCIe environment

By leveraging years of experience in protocol analysis tools for emerging markets, Teledyne LeCroy's PCI Express protocol analyzers blend sophisticated functionality with practical features to speed the development of PCI Express IP cores, semiconductors, graphics, servers, workstations, bridges, and switches.

Product Features

  • Trace Expert Analysis and Report - NVM Express, SATA Express performance, statistics and analysis
  • Powerful & Intuitive CATC Trace - Faster interpretation and debug of PCI Express traffic.
  • Expert Software Extensive Decoding - Understand the protocol completely with accurate and reliable decoding of TLPs (Transaction Layer Packets) and DLLPs (Data Link Layer Packets) and all Primitives for PCI Express.
  • LTSSM Flow Graph - Look at the trace from the LTSSM State machine perspective to understand how the link is behaving. Quickly see if states are getting stuck or if the link is going up or down. Navigate the trace using the state bubbles that are hyper linked to the trace.
  • Compact Trace View - Compact the trace to get a better overall understanding of what is happening in the entire trace.

  • Advanced Triggering/Filtering - Find Errors fast by isolating important traffic, specific errors or data patterns. Understand transactions more clearly by removing non-essential fields from the trace.
  • Flow Control View - Check on credit behavior between Root complex and endpoint transactions. See the credit decrement and credit updates in the trace with clarity.
  • Intelligent Reporting - Quickly identify and track error rates, abnormal link or timing conditions, display configuration space, and protocol specification details.
  • One Button Error Report - View the entire trace for PCI Express Errors. Navigate to each error by clicking on the error indicated.
  • Dword to Transaction Level Viewer - See and understand Symbol, Packet, Link and Split Transaction levels of the PCI Express protocol.
  • Monitoring and Link Utilization - Troubleshoot throughput, link utilization, and bandwidth issues.
  • BitTracer Software Option - Records the bytes as they come across the link. Allows debugging of PHY layer problems. Gives protocol analyzer the best of both worlds; a logic analyzer format and decoded protocol analyzer format.

    • Quickly identify new PCIe 3.0 start tokens

    • See the new 128/130 bit encoding structure in PCIe 3.0 packets

  • Auto Sense Link - Analyzes all traffic negotiation between two devices of different lane widths.
  • NVMExpress(PCIe SSD) Specification Decoding and Analysis - NVMe Initialization Decoding
  • Decode NVMe Commands
  • Analyze NVMe Queues
  • NVMe Multiple Pointer Based Transactions
  • NVMe Power Management
  • Extract the PCIe SSD Base Address automatically
  • SRIOV Decode Support - Analyze Single Root IO Virtualization enabled devices.
  • MRIOV Decode Support - Analyze Multi Root IO Virtualization enabled devices.
  • Lane Swizzling - Accommodates specialized or unique board layouts for MidBus connections.
  • Deep Buffer Recording Capacity - Capture long recording sessions for analysis and problem solving up to 8 GB (4 GB in each direction).
  • CRC Checking - Know that info being displayed is accurate.
  • High-speed Interface Ports - No complicated setup required, with 1 Gb/s Ethernet and USB 2.0 ports available.
  • Downloadable Trace Viewer - Share and annotate trace recordings within a development team.

 

Host Requirements Windows XP or Vista; Intel Pentium II processor or greater; USB Port or 1Gb/s Ethernet
Recording Memory Size 8 GB for trace capture, timing, and control information
Power Requirements 100–240 VAC, 47–63 Hz (universal input), 480 W maximum
Connectors  AC power, external trigger (TRIG IN/OUT, SMA), USB host computer connection, Ethernet
Power On/Off
Manual Trigger Forces a trigger event when pressed
Dimensions 15.45 x 5.39 x 14.3 inches (40.4 x 38.6 x 9.6 cm)
Net Weight 17 lbs
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