quantumdata M42de Video Analyzer/Generator

The quantumdata M42de is a highly configurable platform for testing DP 2.1 (and 1.4) source and sink devices with quick real-time views as well as full capture of main line video including meta data and AUX transactions. Invaluable for testing silicon development boards, displays, docking stations, hubs, USB-C adapters, retimers and extenders. The video generator offers a large library of standard video timings and test patterns necessary for easy verification of next generation displays. A complete API for automated testing is now available for compliance testing.

The M42de supports generation and analysis of the DisplayPort data streams through the user-friendly Video Protocol Suite Manager. The M42de features an embedded CPU (linux-based) that operates as a stand-alone platform by connecting an HDMI monitor plus keyboard/mouse. Optionally an external laptop can be connected directly to the unit (via RJ45 LAN port) and control the analyzer as a remote PC. Both approaches provide fast access to captured video logs up to 8GB in size. The Passive Probe feature based on Teledyne LeCroy’s cutting-edge T.A.P.4™ technology, enables full monitoring of the DisplayPort Main Link and AUX Channel between two DisplayPort devices at the full 20 Gb/s lane rates. For developers of Embedded DisplayPort (eDP), the M42d offers fast link training, alternate scrambler seed, Advanced Link Power Management (ALPM) and Tx backlight control.

• Equipped with USB-C ports and new enhanced full-size DisplayPort (DP80) connectors for Tx and Rx functions
• Fully supports UHBR sink and source testing at 10Gb/s, 13.5Gb/s and 20Gb/s lane rates with 128b/132b line coding
• Supports a broad range of compliance testing for HBR3 and UHBR source, sink and branch devices in accordance with VESA DP 2.1 compliance test specifications
• View incoming video and metadata (including DSC compressed) from a source device
• Capture and decode video, protocol, control packets including Display Stream Compression (DSC) and Multi-Stream Transport (MST)
• Custom video generator can test displays at HBR and UHBR lane rates with large format and image library
• Configure link training parameters to test display’s handling of link training
• Generate Display Stream Compression (DSC), select patterns and configure slices and video parameters
• View and edit EDID and DPCD registers
• Monitor AUX Channel transactions while emulating a DP 1.4 or DP 2.1 source or sink
• Exclusive: T.A.P.4 passive monitoring mode provides visibility to Main Link and AUX Channel traffic for debug of interoperability issues between real DP 2.1 devices
• Test source and sink devices with Panel Replay capability
• Python-based automation API allows running compliance and custom verification tasks in unattended mode
• Support for LTTPR in non-transparent mode for 128b/132b at UHBR rates and 8b/10b encoding for lane rates up to HBR3
• View Power Delivery (PD) protocol negotiations for USB-C DP Alt Mode
• qdPrime™ automatically test a huge range of DisplayPort configurations

Source Link Layer Compliance

The DP source link layer compliance option is ideal for pre-testing HBR3 or UHBR-capable devices prior to submission to an Authorized Test Center. Pre-testing is considered a critical step in assuring a smooth certification process. The optional compliance test packages allow users to view detailed results and help pinpoint the cause of any failures. AUX channel traces are also saved during Link Layer testing to provide a reliable record of AUX transactions.

Sink Link Layer & EDID Compliance

The DP sink EDID/DisplayID and Link Layer compliance option fully supports DP 1.4 certification and a growing list of DP 2.1 tests. Covering dozens of test cases and hundreds of assertions, the link layer CTS package is foundational for any engineering verification test effort. With essential tests for critical functions including training, forward error correction (FEC), power management and multi-byte AUX transactions, this base package is the starting point for comprehensive test coverage.

LTTPR Source, Sink & Retimer Compliance

The quantumdata M42de provides automated, one-button testing of Link Training Tunable Phy Repeater (LTTPR) compliance. Now with specific tests for HBR3 and UHBR-capable DisplayPort source, sink and retimer devices, the M42de mimics real LTTPR network behaviors to verify that sources can properly configure and link train in both transparent and non-transparent modes. Simple pass/fail reports are automatically generated and detailed AUX logs are captured which are invaluable for understanding issues during clock data switch phase, equalization, or inter-lane alignment.

The qdPrime test suite provides a huge library of quantumdata proprietary tests designed to verify DisplayPort functionality and interoperability for both sources and sinks. This optional feature systematically tests different combinations of lane-width, link rate, timing, refresh-rate, color-space, and bit depth to ensure devices operate properly with the DisplayPort 2.1 ecosystem. Each individual test generates a pass/fail result with detailed logs to provide a repeatable snapshot of device interoperability.