1182 Charge Analog-To-Digital Converter


The VME Model 1182 features 8 channels of ADC with current integrating negative inputs and a common gate. It offers 12-bit operation with a sensitivity of 50 fC/count and a conversion time of 16 µsec.

Gated integrating ADCs provide high flexibility. The use of gated integrators allows the shaping time of the system to be determined at run time. The same ADC can be used to encode photomultiplier and chamber signals or to sample slowly varying signals. DC-coupled gated integrators are best suited to high rate applications, especially when a wide dynamic range is required.

The 1182 ADC is a standard VME 6 U x 160 mm single-width module. The internal memory is read/writable from VME. The control register, CSR0, is read/writable from VME at all times.

The optionally available CERN Jaux Dataway is a 30-pin standard DIN type connector mounted between P1 and P2. The Jaux Dataway can provide differential gate and clear, as well as -2 V, -5 V, +15 V, ground and clean earth.


Input Circuit

The input circuit of the 1182 employs charge multiplexer (MIQ401 QMUX) monolithic circuits. The QMUX is designed to do an integrate-and-store function as well as multiplexing the output to a common amplifier and ADC.

Conversion Technique

After gating, charge is held in the QMUXs and is sequentially multiplexed into a rapid conversion ADC. Digital data is transferred to the readout buffer and is promptly ready for readout.


The readout is in accordance with the VME Standard (ANSI/IEEE-1014), so modules may be read out via Stan dard VME hardware (e.g., VME Master).



VME Device Type:
A24/D16/D08 Slave.

Base Address: Switch selectable, A16-A23.

Address Modifier Codes: AM = 39, 3B, 3D, 3F.

DTACK: On valid address and no internal error.

BERR: Monitored to insure proper operation with VME specification.


AD16-AD23 &shyp; indicates address switch setting. ADR &shyp; yellow LED blinks when module is addressed. CIP &shyp; blinks when a conversion is in progress. PWR &shyp; red LED which indicates +12 and +5 and -5 present.


Test Conditions:
Unless otherwise stated: 25° C; 1.5 µsec gate width; 2 µsec MPI.

ADC Type: Gated, current integrating, 12 bits.

Signal Inputs: 8 input channels , Lemo connector, 50 ohm. Protected to ±100 V for 1 µsec. Operating Region is +10 mV to -1.5 V for specified linearity (+0.2 mA to -30 mA into 50 ohm).

Gate Input: NIM signal, bridged Lemo connector, Hi Z input. Width: 50 nsec to 2 µsec. Requires 50 ohm termina tion.

Fast Clear: NIM signal, bridged Lemo connector, Hi Z input. Clears module and prepares it for a new Gate. ADC results settle to within ±2 counts in less than 650 nsec. Requires 50 ohm termination. Minimum pulse width 50 nsec.

Conversion In Progress (CIP) Output: NIM signal, Lemo connector, 50 ohm. Front-panel output to indicate an A-to-D conversion is occurring or that module memory is full.

Cern VMEbus V430 Option: The model 1182J is a standard option to the 1182 which provides compatibility to Cern V430 specification. An additional Bus connector is added (Jaux) which provides for -2 V, -5 V and +15 V as well as gate and clear signals.

Pedestal: 300 ±200 counts. Pedestal spread reduces with narrower gates. This allows the user to lower the nominal value with an on-board trim pot. Pedestal correction may take place in the VME Master during data readout.

Full Scale Charge: 200 pC nominal, 170 pC minimum (at maximum sensitivity and maximum pedestal).

Sensitivity: 50 fC/count ±3%.

Integral Linearity: < ±(0.25% of reading +2) counts.

Differential Non-Linearity: ±0.9 LSB, largest variation over all codes for a typical unit.

Noise: 0.8 counts R.M.S. typical, 2 counts maximum. Tested with no signals connected and a constant conver sion rate.

Interchannel Isolation: 75 dB typical, 60 dB minimum.

Temperature Coefficient: < ±(0.1% of reading +1 count)/°C; (inputs unconnected or driven by a high imped ance source).

Long Term Stability: ±(0.25% of reading +1 count)/week.

Rate Effect: (Variation in pedestal with gate-clear repetition rate for rates between 1 Hz and 10 kHz.) Board average: 1.5 counts typical 2.5 counts max. Individual channel: Board average ±1.5 counts.

Conversion Time: 16 µsec.

Measure Pause Interval: 400 nsec to 6.5 µsec. Allows a fast clear to be applied to the module before the analog-to-digital conversion starts. Factory set to 1.5 µsec via board-mounted potentiometer.

Packaging: 6 U x 160 mm, single-width VME module in conformance with VME Specification (ANSI/IEEE -1014C).

Operating Temperature: 10° to 50° C.

Storage Temperature: -30° to 85° C.

Maximum Humidity: 80% non-condensing at 30° C.

Power: 1182 100 mA at +12 V; 2 A at +5 V. 1182J 100 mA at +12 V; 2 A at +5 V; 75 mA at -2 V; 75 mA at -5 V; 50 mA at +15 V.

Ordering Information

1182 &shyp; Standard ADC
1182J &shyp; Compatible to Cern V430

Address Structure

CSR0 Bit Definitions

Copyright© June 1996. LeCroy is a registered trademark of LeCroy Corporation. All rights reserved. Information in this publicaction supersedes all earlier versions.