- DDR4 test coverage as described by the JESD79-4 JEDEC specification
- Leverages industry leading serial data algorithms for jitter breakdown and eye rendering
- Fastest way to gain confidence in your DDR4 interface by measuring a large number of cycles and reporting statistically relevant results
- Maximize signal integrity with De-embedding and Virtual Probing
- Fully annotated worst case measurement screenshot captured and displayed in report including trace labels and pertinent voltage levels
- Stop on test/failure capability allows the user to pause at a particular test and review the measurement on the oscilloscope display
Greatest Confidence and Debugging Capabilities of Any DDR4 Solution
Teledyne LeCroy’s DDR4 compliance test package automatically measures a large number of cycles in a short period, performing several thousand measurements in the same time competitors perform less than one hundred. This capability is critical to deliver statistically meaningful results and ensure confidence that the true maximum and minimum points have been caught without requiring multiple acquisitions. Additionally, Teledyne LeCroy’s DDR4 compliance test package easily enables system debug which is crucial for DDR4 development efforts. By using the “Stop on Test” feature the user can pause testing after each individual test and leverage the variety of debugging tools Teledyne LeCroy has to offer. Upon completion, testing can be seamlessly resumed with one click of a button.
De-embedding and Virtual Probing
With the speeds DDR4 is approaching, the probing of the signals under test is becoming increasingly important. In order to obtain the best signal quality and minimize reflections, the ideal probing location is directly at the ball grid array (BGA); however, in reality this is not practical. Teledyne LeCroy provides a variety of software tools which can be used to improve the DDR probing experience to maximize signal integrity. The VirtualProbe package allows the user to virtually move the probing location to the DRAM BGA, where the probe cannot be physical placed. Additionally, VirtualProbe can be used to remove any effects of the probe or interposers through de-embedding. Furthermore, the VP@Rcvr (Virtual Probe at Receiver) math function can be used to model the circuit of the DIMM to reduce reflections in the signals under test. The use of these software options will ease the difficulty of testing DDR4 signals.
DQ Input Receiver Compliance Mask
For the first time the DDR4 specification includes a compliance mask for the DQ input signal which replaces some of the traditional setup and hold time measurements. QPHY-DDR4 enables the user to test DQ input signal against this mask and will report any mask hits. This eye diagram is also used to calculate the VIHL_AC peak to peak requirement.
The DDR4 specification requires clock jitter to be separated into random and deterministic components, which is a first for DDR specifications. QPHY-DDR4 leverages industry leading serial data algorithms to perform the jitter breakdown for tJIT(per) and tJIT(cc). In addition to these tests, QPHY-DDR4 will test average clock period, absolute clock period, average high/low pulse width, absolute high/low pulse width, duty cycle jitter, and cumulative error over n period tests.
tDQSQ verifies the skew between DQS and the associated DQ within a read burst. QPHY-DDR4 will perform this measurement on every DQ transition within a read burst and calculate the maximum, minimum, standard deviation, and average values. Upon completion each test will display a fully annotated “worst case measurement” screenshot which includes trace labels for the signals under test and relevant voltage levels.
SRIN_dIVW, the DDR4 definition for input slew rate, measures the slew rate on every rising and falling edge within a write burst. QPHY-DDR4 will measure every transition within each write burst in the acquisition providing statistically meaningful results in a short period of time. In this case over 1,000 slew rate measurements were performed which ensures that the true maximum and minimum points have been caught without requiring multiple acquisitions.
QualiPHY is designed to reduce the time, effort, and specialized knowledge needed to perform compliance testing on high-speed serial buses.
- Guides the user through each test setup
- Performs each measurement in accordance with the relevant test procedure
- Compares each measured value with the applicable specification limits
- Fully documents all results
- QualiPHY helps the user perform testing the right way—every time!