Teledyne LeCroy's new SimPASS software applications bring all the analytical and decoding power of a protocol analyzer to the pre-silicon stage of simulation design verification. Decode, troubleshoot and debug your simulation code before taking the expensive step of committing the design to silicon.
SimPASS allows RTL simulation vector files (that describe data traffic in the pre-silicon phase) to be displayed and analyzed in the same way as hardware-derived trace files in the post-silicon phase. By extracting features that show potential flaws in data and transaction packets from the data stream, SimPASS enables developers to more completely test and debug the logic design before committing the design to silicon, a major advance in eliminating design flaws that can cause expensive and time-consuming redesign. Major issues facing developers can be quickly discovered, tracked to their source, and resolved, resulting in significantly faster time-to-market and lower development costs in new product development.
SimPASS works by importing raw symbol traffic as captured in an RTL simulation. Developers can export RTL simulation vector files from leading electronic design automation (EDA) compliance tools. The symbol traffic files are directly analogous to a trace file captured from hardware, and can be analyzed by SimPASS, helping to determine potential protocol errors. This provides important advantages in identifying and troubleshooting logic design flaws during the simulation and functional verification process, by using the powerful data displays and "drill down" capabilities of the CATC Trace displays in quickly locating the source of each error. During any redesign cycle, fixes for bugs (identified in the previous cycle using Teledyne LeCroy's trace analysis software) can be verified by testing the fixes during simulation using the SimPASS software.