The Voyager M3i is Teledyne LeCroy’s 6th generation USB protocol verification platform designed for the next evolution of universal serial bus known as SuperSpeed USB. Leveraging Teledyne LeCroy’s extensive expertise in high-speed serial data analysis, the Voyager provides 100% accurate protocol capture of both USB 2.0 and 3.0 at data rates up to 5 Gb/s.
Explore Voyager M3i
Teledyne LeCroy's flagship validation platform for USB 2.0 and 3.0 verification provides 100% accurate protocol capture at data rates up to 5 Gb/s
Teledyne LeCroy's original validation platform for USB 2.0 and 3.0 provides 100% accurate protocol capture at data rates up to 5 Gb/s
Ultra-portable SuperSpeed USB analyzer delivers market leading accuracy at an extraordinary price
The Mercury T2 analyzer is the industry's smallest hardware-based USB 2.0 analyzer supporting low, full and hi-speed USB signaling.
Teledyne LeCroy has developed six generations of its industry leading USB protocol verification system since the introduction of USB in 1995. Each successive generation of the Teledyne LeCroy USB analyzer family has built upon the previous knowledge and expertise. Today, Teledyne LeCroy offers a broad range of USB test systems with unprecedented functionality, accuracy and user friendliness. The enormous cost of discovering problems after a product is released far outweighs the investment in Teledyne LeCroy's de-facto standard USB analysis tools. Their use improves the speed and efficiency of the debug, test and verification for USB semiconductor, device, and software vendors. Analyzers or bus "sniffers" also play an essential role in avoiding costly interoperability problems by allowing developers to verify compliance with the USB specification.
Consistent with the growing popularity of digital media, the USB-IF announced USB 3.0 in late 2007 targeting 10X the current USB bandwidth by utilizing two additional high-speed differential pairs for "SuperSpeed" transfer mode. The USB 3.0 specification was released in late 2008 and commercial products began shipping in late 2009. Teledyne LeCroy has pioneered the development of verifications systems for this new technology. The only company that offers a complete line of USB 3.0 test solutions covering transmitter test to protocol test, and every step in between, Teledyne LeCroy helps developers achieve their goals of performance, quality, reliability and time-to-market for SuperSpeed technology.
USB Technology Overview:
USB, or Universal Serial Bus, is a connectivity standard that enables computer peripherals and consumer electronics to be connected to a computer without reconfiguring the system or opening the computer box to install interface cards. The USB 1.0 specification was introduced in January 1996. The original USB 1.0 specification had a data transfer rate of 12 Mbit/s The first widely used version of USB was 1.1, which was released in September 1998. It provided 12 Mbps data rate for higher-speed devices such as disk drives, and a lower 1.5 Mbps rate for low bandwidth devices such as joysticks. USB 2.0 specification was released in April 2000 and was ratified by the USB-IF at the end of 2001 to develop a higher data transfer rate, with the resulting specification achieving 480 Mbit/s
USB today provides a fast, bi-directional, low-cost, serial interface that offers easy connectivity to PCs. A hallmark for USB operation has been the ability for the host to automatically recognize devices as they are attached and install the appropriate drivers. With features such as backward compatibility with previous devices and hot "plug-ability", USB has become the de-facto standard interface for various consumer and PC peripheral devices. The USB standard allows up to 127 devices connected to a Host System. USB designates low, full, high-speed connectivity between devices compatible with the 2.0 specification. Most full speed devices include lower bandwidth mice, keyboards, printers, and joysticks. The use of high speed USB has exploded with the rapid growth in digital media in the consumer electronics market including media players, digital cameras, external storage and smart phones.
SuperSpeed USB is designator for links operating at the 5 GHz frequency and compatible with the USB 3.0 specification. SuperSpeed USB provides a high performance connection topology for applications that utilize larger files or require higher bandwidth. SuperSpeed USB is backward compatible with USB 2.0, resulting in a seamless transition process for the end user. SuperSpeed USB offers a compelling opportunity for digital imaging and media device vendors to migrate their designs to higher performance USB 3.0 capable interface.
NEC/Renesas was the first chip vendor to introduce host controllers for USB 3.0 (5/18/2009). The first motherboards featuring USB 3.0 ports from Asus and Gigabyte followed in late 2009. In the first half of 2010, dozens of SuperSpeed devices began shipping as vendors rushed to deliver solutions using the 5Gbps signaling speed of USB 3.0. Expect mass adoption into high-bandwidth applications in late 2010.
From its emergence in 1995 as a low-cost connection interface for keyboards and mice, USB has steadily expanded its presence in computing and consumer electronics to become the most popular peripheral interconnect in history. USB continues to be dominant for the following reasons:
- Mature, proven technology
- Backward-compatible and low cost
- Easy plug and play operation
- Data transfer speeds suitable for a variety of applications
As evidenced by USB popularity, several extensions of the technology have been introduced to try and capitalize on its installed base/ popularity. An example of this extension, which is supported and approved by the USB Implementers Forum (USB-IF), is USB On-The-Go (OTG). Designed to allow portable computing devices, such as cell phones and digital cameras, the ability to connect to other USB devices as either a host or peripheral, OTG promises improved interoperability for an enormous number of USB enabled devices.
In addition, there are now dozens of USB device classes addressing everything from health care systems to isochronous video applications. Mass storage remains one of the most popular USB applications as consumers have embraced all types of digital media. The T10 committee has now finalized USB Attached SCSI (UAS) protocol which enables several significant improvements over legacy mass storage protocols including command queuing and streamed IO. Of particular interest is the new battery charging specification which provides a standard mechanism allowing devices to draw current in excess of the USB specification when connected to wall chargers or fast charging host controllers. In addition to the traditional data interchange application, the battery charging specification has solidified USB's dominant role as the interface of choice in the portable electronics market.
USB was initially introduced as a host to peripheral interconnect with the goal of putting most of the intelligence on the host-side. The OTG specification added an optional peer-to-peer capability to devices but had limited adoption to date. So the vast majority of USB devices typically fall into 2 categories:
- All devices designed to attach to a host (examples)
The role of the host controller (plus software) is to provide a uniform view of IO systems for all applications software. For the USB IO subsystem in particular, the host manages the dynamic attach and detach of peripherals. It automatically performs the enumeration stage of device initialization which involves communicating with the peripheral to discover the identity of a device driver that it should load, if not already loaded. It also provides device descriptor information that drivers can use enable specific features on the device. Peripherals add functionality to the host system or may be standalone embedded operation. When operating as a USB device, peripherals act are slaves that obey a defined protocol. They must react to requests sent from the host. It's largely the role of PC software to manage device power without user interaction to minimize overall power consumption. The USB 3.0 specification redefines power management to occur at the hardware level with multiple power states designed to reduce power usage across the IO system.
The Voyager M3i is Teledyne LeCroy's 6th generation USB protocol verification system designed for the next evolution of universal serial bus known as SuperSpeed USB. Leveraging Teledyne LeCroy's extensive expertise in high-speed serial data analysis, the Voyager provides 100% accurate protocol capture of both USB 2.0 and 3.0 at data rates up to 5 Gb/s.
This multifunction validation platform is available with an integrated exerciser capable of both 2.0 and 3.0 host and device emulation. In addition to error injection and compliance verification, the exerciser can emulate a SuperSpeed endpoint and intelligently respond to enumeration requests. From fault recovery to performance optimization, the Voyager system can help assure that devices deliver excellent compatibility and throughput.
Voyager USB 3.0 Introduction series of video demos
The Voyager analyzer front-end leverages custom circuitry from Teledyne LeCroy's 5Gb/s PCI Express analyzer to provide fast-locking and uncompromised accuracy for USB 3.0 recording. SuperSpeed USB devices utilize hardware based power management with devices frequently entering power suspend mode. While in-line, the Voyager system will detect and seamlessly recover from electrical idle while accurately showing all bus and power state transitions time-stamped within the display.
The front end of the Voyager analyzer features native 3.0 connectors that bifurcate USB 2.0 and 3.0 electrical signals to provide loss-less capture of traffic from both links simultaneously. Concurrent high-speed and SuperSpeed recording allows end-to-end viewing of data transfers across a USB 3.0 hub. The system can operate as a USB 2.0/3.0 analyzer; and is also available in a 2.0-only configuration that is upgradeable to 3.0.
The Voyager M3i platform includes 4GB of recording memory plus USB and Gbe links for uploading recorded traffic to the host PC. Fast access to captured traffic is now possible thanks to sustained data transfers of 600Mbit per second over the Gbe link. Both the analyzer and exerciser can utilize slow clocking (fractional) or external clock sources (as low as 1Mhz) for testing with FPGA-based prototypes or emulators that require ultra low-speed data acquisition. More
The heart of the Voyager verification system is Teledyne LeCroy's revolutionary BusEngine™ technology. This state-of-the-art protocol processing core incorporates a real-time recording engine and configurable tools to selectively monitor and record SuperSpeed USB traffic. Field upgradeable firmware allows the BusEngine to evolve and support new features or future changes to the USB specification.
The analyzer and exerciser also include optional SMA differential Input/Output lines as an alternate interface for taping between early development boards. Using a high-grade co-ax connection for the USB 3.0 link allows developers to isolate problems that could be affected by the SuperSpeed connectors.
6th Generation Analysis Software
The Voyager utilizes the legendary CATC Trace - the industry's de facto standard for USB 2.0 protocol analysis. The trace viewer software uses colors and patterns to train the eye to understand information faster. When recording mixed traffic upstream from a SuperSpeed hub, Legacy 2.0 and 3.0 packets are labeled and interleaved in a single display. Each event is shown on a separate row with every field labeled and color coded.. Traffic from the logical 2.0 & 3.0 channels can be individually filtered, searched or exported from the trace. The USB Transfer level can be expanded and collapsed to show the packet layer including all link management packets (LMPs) and flow control symbols.
Raw Debugging Power
The Voyager includes a special Link Tracker mode that captures every transition and presents raw 10-bit data patterns chronologically with timing resolution of 2ns. Designed to assist with low-level debugging, all ordered sets including training sequences and inter-packet symbols can be displayed in raw 10-bit, 8-bit, scrambled, and unscrambled Hex format. Symbol-to-symbol timing measurements are possible with a single click.
- CATC Trace Analysis Software System – Expand / Collapse transfer layer for faster interpretation of USB traffic
- Capture / Analyze 3.0 & 2.0 traffic concurrently – Record 2.0 and SuperSpeed data path to test & debug USB 3.0 host & hub operation
- Integrated 3.0 analyzer / exerciser (single box) – Multifunction system with 3.0 and 2.0 device or host traffic generation
- 4GB Recording Capacity - Capture long recording sessions for analysis and problem solving
- Raw bit Recording / 10-bit error detection – view and correlate low-level 10-bit symbols to higher-level packet structures
- Detects over 40 Link & Protocol errors – Critical link and timing errors are automatically detected and flagged in the trace
- 2ns timing resolution - extremely accurate timing resolution allows precise measurement of link layer handshaking
- External Trigger In / Out – Use the Teledyne LeCroy Voyager to identify any packet and toggle a scope or logic analyzer (via SMA connectors)
- Fully supports SSC and Data scrambling - Fast Locking and Accurate capture on 5Gbps signals
- Hardware Triggering – Trigger on both 2.0 or 3.0 protocol events to isolate important traffic, specific errors or data patterns
- Comprehensive Device Decoding - SCSI Mass Storage, 3.0 Hub, PTP/Still Image, Printer, PictBridge, Media Transfer Protocol (MTP), and all popular USB device classes
- Hardware Filtering - Automatically exclude non-essential and redundant symbols including Idles, TS1, TS2, SKPs, and LFPS sequences.
- Intelligent Reporting - Automatically report event metrics and flag over 20 common USB 3.0 protocol errors
- Sophisticated Viewing - View TLP messages and headers, plus logical transaction and transfer layers of the USB protocol
- Gbe or Hi-Speed USB upload – Sustained transfer rates of 600Mbps over Gbe provide instant access to captured data
- SMA-input differential probing - alternate connector interface allows taping between early development boards if native connectors are unavailable More
- Slow clock / External clock Input – Adjustable signal frequencies for synchronizing analyzer timing with prototype & validation boards
- Loopback and Compliance Mode – Exerciser system provides special console for initiating loopback and compliance mode
- Link Training and Timing Views - LTSSM flow diagram and chronological views linked to trace display
- Power Tracker™ Option - Graphs Power & Current draw for VBus devices synchronized to the trace data
- 13 Month Hardware Warranty - Protect your investment with industry leading support and warranty
The Voyager provides hardware triggering to pinpoint protocol events of interest. Trigger events can be specified at the lowest levels including bus states and ordered sets (Link up, SKP, etc...) or header fields including route strings or packet types (ACK, EPRDY, etc….). Voyager's graphical drag-and-drop interface makes setup easy. Users can define trigger logic that monitors multiple sequential event trigger scenarios that include SCSI operations, counters, loops and timers all within a multi-level sequence.
Real Time Filtering
SuperSpeed data transfers at 5 Gb/s can fill memory buffers in an instant making event filtering critical for efficient debug. The Voyager analyzer can filter unwanted traffic from the buffer in real-time by discarding redundant patterns such as SKPs, idles, and training sequences. Filtering logic can also include transaction layer packets with added criteria like direction or port number.
The Teledyne LeCroy Voyager can detect and flag real protocol errors including logical link and timing errors. At the lower layers, training sequences and link commands are automatically verified for proper formatting. The Spec View displays header fields in hex or binary and also marks errors in red.
Integrated Exerciser Option
A comprehensive exerciser capability with support for both USB 2.0 and 3.0 traffic generation is built in to the Voyager platform. The exerciser option allows users to transmit custom packets over standard USB cables with low-level control of headers, payloads, timing, and link states. Featuring Voyager ReadyLink™ and Transaction Engine™ the exerciser includes full function link and transaction layer state machines that automatically handle all USB 3.0 handshakes. ReadyLink maintains link synchronization, flow control and header acknowledgements. The Transaction Engine manages NRDY retry conditions allowing the Voyager to operate at full line rate and correctly respond to the DUT as defined by the specification. . Overrides allow these behaviors to be altered such as shortening LFPS and link training signals, or delaying handshake packets. The Exerciser is seamlessly integrated with the Protocol Analyzer, making the Voyager system a complete test and development solution for engineers validating USB protocol. More
USB Device Decoding
The Voyager software performs full decoding of USB device class traffic with both automatic and manual assignment of decodes to individual endpoints. The Voyager offers full support for Bulk Only Transport and USB Attached SCSI operations including command queuing. From OTG, to CCD, to Video class, Voyager provides the most comprehensive decoding available. It also supports vendor specific decoding for developers interested in automatically showing proprietary commands in the trace view.
Complete list of USB Decodes (Click to Expand ↓)
- CDC (Communications Device Class)
- Direct Line Control Model
- Abstract Control Model
- Telephone Control Model
- Multi-Channel Control Model
- CAPI Control Model
- Ethernet Networking Control Model (EEM)
- Network Control Model (NCM)
- ATM Networking Control Model
- Wireless Handset Control Model
- Device Management Model
- Mobile Direct Line Model
- Mobile Broadband Interface Module (MBIM)
- OBEX Model
- CDC Data
- HID (Human Interface Device)
- Monitor (HID extension)
- Physical Interface
- Power (HID extension)
- HUT (HID)
- Point of sale Devices (HID extension)
- Mass Storage
- USB Attached SCSI (UAS)
- Still Imaging Class
- MTP Class Decoding Extension
- Video Class
- USB Video 1.5 (UVC)
- USB Video 1.1
- Miscellaneous Classes
- Host Wire Adapter
- Cable Based Association Framework (CBAF)
- Device Wire Adapter
- Interface Association Descriptor
- IrDA Bridge
- Personal Healthcare (PHDC)
- Test & Measurement
- 00 - USB Test and Measurement Device
- 01 - USB Test and Measurement Device conforming to the USBTMC USB488
- USB3 Vision
- USB Vision Event
- USB Vision Stream
Find The Issues Fast
The Voyager software provides many mechanisms to measure and report on USB 2.0 and 3.0 protocol. With the Traffic Summary display, users can evaluate statistical reports at a glance or navigate to individual events. Users may select transaction packets to view ACK/NAK or Device Notification events, then jump to each occurrence with a single keystroke. Reports are available showing link throughput and flow control metrics. Higher level events are also tracked and reported at the logical USB Transfer level. The error report shows a range of protocol violations - from invalid CRCs to framing errors.
The LTSSM View provides an interactive USB 3.0 state machine diagram. Each state change is shown graphically and is hyperlinked to the trace display. The link state timing view shows the same information in a time-line format.
Bus Utilization graphs show data and packet length, bus usage by device in a histogram format. The Bandwidth calculator automatically calculates the time delta between two points in the trace. Fast Search and Find options allow users to navigate to specific packets, errors and any data type within a trace file. The CATC Trace supports filter and hide commands, to temporarily remove irrelevant data from the display for more efficient viewing.
Optimize vBus efficiency with PowerTracker™
The Voyager M3i Power Tracker option offers a unique monitoring capability for Vbus power draw. Power information is sampled and displayed graphically in a time line format and is synchronized to the trace allowing users to verify power state transitions at the protocol and electrical layers. More
Since 1996, Teledyne LeCroy has been a key provider of tools for the USB ecosystem. The Voyager system leverages countless hours of research in high-speed serial data analysis to create the most reliable and accurate USB 3.0 analyzer system available. Combined with the exerciser option and the CATC Trace expert software, the Voyager platform alleviates developers from tedious byte-level analysis and lets them focus on quick resolution of protocol layer problems.
|Product Model|| ||Teledyne LeCroy Voyager USB 3.0 Pro Analyzer System|
| || || |
|Basic Functions:|| || |
| ||Protocol(s) Supported|| ||USB 1.0, 1.1, 2.0 & 3.0|
| ||Protocol Analyzer|| ||Yes|
| ||Protocol Exerciser|| ||Yes|
| ||Other|| ||N/A|
| || || || |
|Host HW Requirements|| ||Pentium II or greater, |
USB 2.0 port
|OS Requirements|| ||Windows XP and Vista |
|Memory Size|| ||4048MB|
|Data Rates Supported|| ||1.2 - 4800 Mb/s|
|Recording Channels|| ||1|
|Data Bus Interface|| ||Half duplex differential (USB 2.0)|
Dual simplex differential (USB 3.0)
|Form Factor|| ||Enclosed Chassis|
|Front Panel Connectors|| ||Analyzer – one (1) USB 2.0 & 3.0 recording channel with USB 3.0 A & B connectors|
Exerciser– one (1) USB 2.0 & 3.0 Generator channel with USB 3.0 A & B connectors
|Front Panel Indicators|| ||Platform LEDs: Power, Status|
Analyzer LEDs: Rec 2.0, 3.0,
Exerciser LEDs: Gen, Rec 2.0, 3.0
| || || |
|Dimensions:|| ||Voyager M3: 12.5 x 11 x 2|
|External Clock Input|| ||MMCX to SMA |
|External Clock Frequencies|| ||1 MHz to 5 GHz|
|Weight|| ||5.4 lbs|
|Power Requirements|| ||90-254 VAC, 47-63 Hz (universal input), 100W maximum|
| ||Alternate Taping Interface|| ||MMCX to SMA differential input / output (record and transmit) |
| ||External Trigger IN/OUT || ||SMA connectors|
| || || || |
|Features|| || |
| ||CATC Trace|| ||Yes|
| ||Field Upgradeable BusEngine|| ||Yes|
| ||SuperSpeed USB 3.0 capture|| ||Yes|
| ||Low/Full/High Speed USB 2.0 capture|| ||Yes|
| ||Integrated Exerciser option|| ||Yes|
| ||Gbe Upload|| ||Yes|
| ||Spec View (3.0 packets)|| ||Yes |
| ||Single state triggering|| ||Yes|
| ||Sequential state triggering|| ||Yes|
| ||Pre-capture filtering|| ||Yes|
| ||Automation API || ||Yes|
| ||On-the-Go (OTG)|| ||Yes|
| ||Raw 10-bit Display|| ||Yes|
| ||Link Tracker|| ||Yes|
| ||Slow Clock Option|| ||Yes|
| ||External Clock Option|| ||Yes|
| ||SMA Differential Input Option|| ||Yes|
| || || || |
|Environmental|| || |
| ||Operating Temperature|| ||32 to 131 F|
| ||Non-operating|| ||-20 to 80° C (-4 to 176° F)|
| ||Operating Humidity|| ||10% to 90% RH |
CrossSync Multi-Protocol Analysis option
CrossSync is Teledyne LeCroy's analyzer synchronization solution that enables time-aligned display of protocol traffic from multiple daisy-chained analyzers. Captured packets are displayed in separate windows that share a common time scale. Navigating the traffic in either direction will scroll to the same timestamp in the synchronized window. When using the CrossSync option, users can access the full complement of analysis capabilities available within each individual Teledyne LeCroy software. Search, reporting, and decoding all operate normally.
Identifying the point where a specific bus event moves over a bridge is nearly impossible without the CrossSync synchronization solution. Now it's easy to use triggering to find the same packet travelling across both busses. Either analyzer can be set up as the trigger master. When the trigger event is detected, the capture on all daisy chained analyzers stops, Each display will show the exact point where the event occurred. It's also possible to define separate trigger events that operate independently for each side of the bridge.
The solution includes a lightweight software control panel that starts and stops recording across daisy-chained analyzers. Users can sync or un-synch traces on-the-fly. The Time Tune feature provides a real time slider for adjusting the offset between displays. This makes it easy to see latency across busses.
The CrossSync control panel is available at no cost and only requires the analyzers to be connected using their on-board Sync ports. This Sync port is built-in to every Advisor T3 and STX M6-1 analyzer. For owners of Teledyne LeCroy's, Summit T3, Voyager M3i, and Sierra -based analyzers, the Sync port is available as an optional expansion board (ACC-EXP-002-X) that can be installed by users in just a few minutes. This allows developers to leverage analyzers already in the lab to help resolve multi-protocol problems at the system level.
The CrossSync option supports a wide combination of Teledyne LeCroy's flagship analyzers including PCI Express Gen 1, Gen 2 and Gen 3, USB 2.0 and 3.0, Serial ATA (SATA) 1.5, 3, and 6Gbps, Serial Attached SCSI 6Gbps, and Fibre Channel 1, 2, 4 and 8Gbps systems.
Teledyne LeCroy Voyager Exerciser Option
Teledyne LeCroy Voyager Exerciser Option
A comprehensive exerciser capability with support for both USB 2.0 and 3.0 traffic generation is built in to the Voyager M3 platform. The exerciser option allows users to transmit custom packets over standard USB cables with low-level control of headers, payloads, timing, and link states. The Exerciser is seamlessly integrated with the Protocol Analyzer, making the Voyager a complete test and development solution for engineers validating USB protocol.
Voyager ReadyLink™ Emulation
ReadyLink is a full function link layer emulation mode built in to the exerciser. It automatically handles all USB 3.0 link training and link flow control to make development of test scenarios fast and easy. SuperSpeed USB devices require a nearly constant stream of low latency responses to manage flow control and link status. By including a complete link layer implementation resident in the exerciser hardware, the emulator operates at full line rate and correctly responds to the DUT as defined by the specification. ReadyLink alleviates the user from the nearly impossible task of manually scripting link layer responses.
Automating link layer responses is essential for providing comprehensive test coverage. It allows validation teams to use the exerciser for bring-up testing or directing the DUT to any logical link state.
By default, the ReadyLink emulation mode will automatically manage:
- Header Packet Acknowledgements (L_GOOD_n)
- Buffer Credit (L_CRD_x)
- SKIPs at required intervals (SKP)
- Link Synchronization
- Responds to LFPS (Polling.LFPS)
- Responds to polling sequence (Polling.RxEQ)
- Responds to TS1 / TS2 handshaking sequence
- Power Management Link Commands
- Responds to LGO_Un (with LAU)
- Responds to LAU (with LMPA)
The ReadyLink emulation can be customized per test script to include various error scenarios, such as header LBADs and invalid link commands. Other errors include:
- 8B10B / CRC Error
- Running Disparity Error
- Corrupt Link Commands
- Corrupt Flow Control (Wrong L_CRD_x, Wrong L_GOOD_n, Drop L_Good_n, etc…)
- Corrupt Header Packet acknowledgement (Send LBAD, LRTY)
- Corrupt Packet Framing (SHP, SDP, END)
At the packet level, users have the freedom to send customized data payloads anywhere within the stream to verify protocol behavior. This makes it easy to insert logic errors, perform corner-case, or stress testing.
Exerciser Control Environment
The Voyager Exerciser includes a text-based scripting interface; but any text editor can be used to create packet level traffic files. For USB 3.0 applications, test scenarios can contain multi-stage traffic generation blocks that include Boolean expressions such as LOOP, DO-CASE, and IF-THEN logical branching. Intelligent script pre-processor allows users to efficiently organize script code and create reusable generation blocks.
A library of predefined test scenarios including source code is provided allowing developers to adapt this substantial test suite to their own specific applications. Users can also create test scenarios by exporting any traffic stream from a previously recorded trace. These stimulus files can be played back bit-for-bit using Teledyne LeCroy’s Exerciser mode. This allows validation engineers to easily recreate problems reported in the field or test specific functionality using a simple trace file.
USB 2.0 Exerciser with Intelliframe
The Voyager 2.0 exerciser is based on Teledyne LeCroy’s legendary USBTrainer exerciser and is backward compatible with existing USBTrainer 2.0 traffic generation scripts. Capable of transmitting low, full, or high-speed traffic, the Voyager 2.0 exerciser also supports both host and device emulation.
For USB 2.0 applications, the Voyager exerciser supports both bitstream mode or Intelliframe mode which adds automatic wait states to the traffic stream. When enabled, the Intelliframe mode will intelligently wait for the appropriate response from the DUT before transmitting the next packet. For example, after issuing an IN, the generator waits for the DATAx packet returned by the device to finish, and then issues an ACK. When NAKs are received the Exerciser can automatically resend the previous packet. Used in conjunction with the Voyager analyzer, makes the Teledyne LeCroy system the most flexible platform for USB development and compliance verification.
Voyager USB 3.0 Compliance Suite
The Voyager USB 3.0 Compliance Suite option allows developers to verify devices are compliant with the USB specification. Integrated with Teledyne LeCroy's Voyager exerciser platform, the Compliance Suite is a sanctioned Link Verification System (LVS) by the USB-IF for performing link layer conformance testing. The Compliance Suite has steadily evolved to include over 200 separate test cases covering hundreds of assertions. For SuperSpeed developers, the chapter 7 Link Layer tests have become an indispensable tool for verifying host, hub and devices properly implement link training, link recovery and power management behaviors. The software also provides chapter 9 framework and MSC coverage for devices to help validate upper layer protocol compliance.
Fully automated, the Compliance Suite loads individual test scripts that generate specific traffic conditions to test individual protocol rules for USB 2.0 and 3.0 devices. The responses from the DUT are automatically captured and analyzed for correct behavior. A pass/fail report is generated in text or HTML. The entire process is automated through a single easy-to-use application which allows users to run individual tests or the entire suite in a single pass. The Compliance Suite provides full source code for all host and device emulation scripts allowing developers to adapt this substantial library for their own custom test cases. Using the Voyager exerciser and the Compliance Suite to verify USB 3.0 conformance will help developers deliver products to market earlier and with higher quality.
Voyager M3 Slow Clock Option
Slow Clock Application Note
The Voyager M3 USB 3.0 Analyzer can support slower than standard clock rates. This option allows users to select clock rates at fractional intervals between 5Ghz and 1Mhz. This option also enables use of external clock sources to synchronize frequency of the Voyager system.
The external clock input is 3.3 volt LVPECL and operates on the USB 3.0 differential signals only. Device setup should be AC coupled at the clock input with a 10 uF ceramic capacitor. When enabled - the slow clock option affects both the analyser (record) and the exerciser (transmit) frequencies.
Voyager M3 SMA Differential Input Option
Teledyne LeCroy’s Voyager M3 platform for USB 3.0 includes an optional SMA Differential Input tapping mechanism for probing SuperSpeed Links. The SMA Input can serve as an alternate interface for taping between early development boards. This eliminates dependencies on USB 3.0 connectors allowing testing to begin as soon as PHY silicon is available. This also allows test teams to remove an additional variable (prototype 3.0 connectors) from the test matrix to help isolate protocol layer issues from possible physical layer problems.
The optional SMA Differential Input can be utilized on host, device or both sides of the SuperSpeed link. It will operate with the analyzer in record mode or can be used with the exerciser additionally to allow transmit and record over this alternate cabling interface.
Voyager USB 3.0 Import Option
Teledyne LeCroy’s Voyager USB 3.0 system provides a unique capability to import comma separated value (.CSV) text files into the CATC trace display. This option is intended for engineers performing pre-silicon verification using Verilog, VHDL, and C++ based development environments. These software-based environments are commonly used to synthesize ASIC and FPGA based prototype hardware.
The use of EDA tools to perform functional verification of SuperSpeed protocol helps users find and fix problems before committing a design to silicon. These verification packages generate USB compliant test vectors which run against RTL or VHDL simulations. The output of these test suites can be imported into the Voyager USB 3.0 software. These simulations will be displayed using the CATC Trace with both host and device traffic clearly marked and time-stamped.
Traffic appears as though it was recorded using the analyzer with full search and decoding capability. This makes it a valuable debugging tool for analyzing and understanding functional verification output.
CATC Sync Card Option
CATC Sync Card is an optional expansion board that installs in the Voyager system (field upgradeable) to allow synchronized recording between multiple Voyager based analyzer systems. The Voyager USB Protocol Suite v3.50 or later allows users to specify trigger event on one Voyager system (master) and then synchronize trigger event and time stamps with the cascaded (slave) analyzer. A single 9-pin serial cable (included) and is used to synchronize timing information between Voyager analyzers.
Voyager M3 Power Tracker for USB 2.0 & 3.0 Option
The Voyager M3 Power Tracker option monitors Vbus power draw and displays voltage graphically in a time line format. This power information is synchronized to the trace allowing users to verify power state transitions at the protocol and electrical layers.
USB 3.0 devices are required to support power management policies to extend laptop battery life and reduce power consumption during idle periods. The Power Tracker adds an integrated multimeter function to the Voyager analyzer. Completely transparent to the system under test, the Power Tracker samples voltage during normal operations. It correlates these physical layer measurements with logical protocol layer events.
USB Embedded Probe
Embedded USB Probe Datasheet
The embedded USB probe allows any Teledyne LeCroy USB protocol analyzer to tap between chip-to-chip USB links using low or full speed Inter-chip signals or standard USB 2.0 signaling.
Inter-Chip USB (IC-USB) specification (Reference A) defines a standard methodology for using USB in chip-to-chip communications. It is used in the embedded systems market as a replacement for i2C to control data transfers between endpoint functions within an embedded device. IC-USB allows vendors to leverage on-board embedded USB host logic to enable faster chip-to-chip communications using USB physical links within a multi-chip PCB assembly.
Teledyne LeCroy’s embedded probe supports tapping these chip-to-chip links using low or full speed Inter-chip signals at all defined IC-USB voltages. The probe can also be used to tap USB 2.0 links at standard 3.3 volt signal levels. The embedded probe utilizes a 4-wire header plug that can be attached as a solder down tap or as flying lead connection attached directly to header pins on the DUT. These probing techniques can be used for both USB 2.0 compliant electrical links or low/full speed Inter-chip links. The USB protocol traffic can be monitored (via the D+/D- wires) by attaching the probe to the "A" port of a Teledyne LeCroy USB analyzer.