LPDDR and DDR Memory Test

WaveMaster 8000HD oscilloscope with HDA125 logic analyzer compliance testing and debugging DDR and LPDDR memories

Fastest Journey From DDR Turn-On Through DDR Compliance Testing

Accelerate the journey to final product with the right tools to quickly test every stage of Double Data Rate (DDR) and Low Power DDR (LPDDR) designs, from initial turn on through JEDEC compliance testing.

Maximize DDR operation from initial turn-on through validation
Accelerate DDR pre-compliance testing and fine tuning
Comprehensive DDR compliance testing

DDR Test to Maximize DDR Operation From Initial Turn-on Through Validation

The right oscilloscope tools support DDR and LPDDR electrical validation, JEDEC compliance testing and debug through multiple stages of design. Teledyne LeCroy reduces bring-up time and helps you find commonly overlooked errors.

WaveMaster 8000HD oscilloscope and Summit T516 analyzer connected to CrossSync PHY interposer for PCIe debugging

Teledyne LeCroy DDR Virtual Probing block diagram of de-embedding interposers and probe location

Teledyne LeCroy DDR eye diagram after removing mid-bus reflections and termination issues.

Teledyne LeCroy Oscilloscopes showing DDR Bus Decode and Trigger for the most DDR and LPDDR Command address signals

Exclusive Toolkit

Probing & Interposers

Virtual Probing

Termination Correction

Decode & Trigger

Establishing basic operation, signal checks and validating responses is foundational during board turn-ons. This means knowing if signals look correct, if the signals are communicating, if the command bus is operational, are voltage and timing settings in the right magnitude of error, do channels show both Read and Write packets. These early steps are critical and require simple, dedicated tools built just for this phase of memory design. This isn’t compliance, it’s more than that.

Do the signals out of the DRAM (Read) or Controller (Write) look correct?
Are initial voltage and timings details in the right locations?
Is the command bus communicating correctly?

Minimizing probe and interposer impacts on your design is critical to maximize DDR signal quality into your oscilloscope. Teledyne LeCroy DH Series Probes are low-noise & low loading active probes with solder-in tips and QuickLink adapters. An interposer can further enhance signal quality by locating the test point close to the ball of the DRAM. Then, the probe and interposer combination can be de-embedded with Virtual Probe.

Explore More Teledyne LeCroy DH Series Differential Probes Explore More Nexus Technologies Interposers Explore More EyeKnowHow Interposers Read Blog Post Tips to Improve DDR Probing Read Blog Post Using Interposers Watch Webinar Top Tips and Techniques for Better DDR Probing and Testing Watch Webinar DDR Debug Scenarios and Virtual Probing

JEDEC requires DDR measurements be performed at the ball of the DRAM (the BGA), or test location #1 in the image. If your probe location is currently at #2 (interposer) or #3 (mid-bus or at a VIA) the probe location can be moved virtually before beginning DDR validation or measurements.

De-embedding .2SP, .3SP and .6SP S-parameter files accounts for T-points with interposers and risers.
Virtual Probing can move the probe point to the memory controller to analyze stressed Read packets.
Remove issues caused by mid-bus probe locations
Read Blog Post Tutorial on Virtual Probing

Probing setup errors, such as reflections, can be confused with DDR design quality. Teledyne LeCroy’s Virtual Probe @ Receiver can be used to eliminate reflections and give you a better picture of your actual DDR design performance.

Remove termination problems with Virtual Probe at the receiver (VP@RCVR).

Teledyne LeCroy's HDA125 Logic Analyzer probes DDR command addresses digitally and conserves analog oscilloscope channels for other signals. DDR protocol decode and trigger can be used on these digitally probed signals to isolate DDR activities and data signals for faster debug. The HDA125 Logic Analyzer supports the highest 8400 MT/s DDR5 CMD address lines for decode and triggering.

Industries only Decode & Trigger up to DDR5
Decode JEDEC's Command Truth Table
Perform better R/W separation, the command bus knows the packet locations
Overlay R/W Visuals on Channels

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Accelerate DDR Memory Test – From Pre-compliance Testing to Fine Tuning

DDR and LPDDR memory operation stability is optimized when voltages, timing and packet parameters are adjusted to their fullest potential in your design. Teledyne LeCroy’s DDR and LPDDR Debug Toolkits help you better understand LPDDR and DDR operation and improve your LPDDR and DDR memory testing.

Teledyne LeCroy DDR Pre-compliance optimization progress testing

DDR Debug Toolkit Features and Capabilities

The DDR Debug Toolkit provides users with capability to build out case-by-case test scenarios with multiple analysis areas, perform decode and triggering on the Command Bus and dive into optimizing design stages with JEDEC specific eye diagrams, mask testing and DDR-specific measurements.

Teledyne LeCroy DDR LPDDR Toolkit has Multiple Scenario Views

Multiple Scenario Viewing

Layout 4 unique testing situations
Before vs. after signal comparisons
De-Embedding vs. Original
Read and Write Strobe-Clock Compares
Measurement Comparisons

Teledyne LeCroy DDR LPDDR Eye Diagram and Mask Passes Testing

Eye Diagram, Mask Testing & JEDEC Specific Measurements

Interactive user Toolkit
Eye Diagram & Mask Testing
JEDEC or custom masks
“Failures” on mask analysis
LPDDR and DDR specific measurements

Teledyne LeCroy DDR LPDDR offers highest Read Write packet separation using the command address

Highest R/W Accuracy

Decode the command address
Know exactly where R & W occur
Upgradable external logic analyzer
Lowest capacitance loading (6x lower than competitors)

Comprehensive DDR Memory Test for JEDEC DDR Compliance and Debug

LPDDR and DDR compliance testing is automated to enable faster test times and reduce errors. Quickly transition between DDR Debug Toolkit root-cause failure analysis and compliance testing using shared test setups.

JEDEC DDR memory test at the ball of the DRAM for DDR compliance test and DDR eye diagram creation.

Full Automation Coverage for JEDEC DDR Compliance Test

Perform compliance tests quickly and efficiently with full reporting of results.

Automates tests with consistent setup and reusable configurations
Validate key electrical and timing parameters at the ball of DRAM, generate eye diagrams
Export results in HTML or PDF formats for easy sharing and analysis
QPHY2-DDR5-SYS
QPHY2-LPDDR5
QPHY-DDR3 (DDR3/3L/LPDDR3)
QPHY-DDR4 (DDR4/LPDDR4/4X)

DDR testing requires DDR compliance test and also DDR PHY debug, with setup details shared between the two different DDR test modes.

Transition Quickly to DDR Debug Toolkit Setup from Compliance Test

DDR Debug Toolkit provides test, debug and analysis tools for the entire DDR design cycle.

Configure all necessary DDR test setup parameters within the DDR Debug Toolkit
Quickly determine optimized test setup for best DDR signal fidelity
Copy DDR Debug Toolkit test setup to QualiPHY 2 compliance test options and save setup time
Watch Video

Validation and Compliance in a Fraction of the Time Using QualiPHY 2

The most intuitive and efficient compliance testing, with offline analysis for more productivity.

Simplified test interface – easy to understand and operate
Compliance on time from anywhere – in lab or offline (outside of lab)
Share test setups from DDR Debug Toolkit

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Download the Latest Teledyne LeCroy DDR Testing Software

Stay up to date with the latest DDR compliance and debug testing features and capabilities for MAUI oscilloscope software and QualiPHY compliance test software upgrades.

DDR Memory Testing Updates and Additions

May 2025

Added support for LPDDR5/5X signals with speeds up to 8533 MT/s

August 2025

Added LPDDR5 and LPDDR5X compliance testing support in QualiPHY 2 framework
DDR5 compliance testing is now supported in QualiPHY 2 framework

Other Recent Updates and Additions

Added more measurements for DDR5 to QualiPHY Compliance Testing software
Added QualiPHY DDR5 System Level compliance testing
Added LPDDR4X support & mask testing
Added QualiPHY compliance testing for LPDDR4X
Updated LPDDR4/4X read/write algorithm for tri-level signals

Download MAUI Software
Download QPHY Software

DDR test showing LPDDR5 Read/Write separation

Recommended DDR Oscilloscope, Probes and Software for DDR Test

Reference the tabs and links below to learn more about the Teledyne LeCroy products for DDR testing and partners for interposers or testing services.

Teledyne LeCroy recommended DDR electrical validation, compliance test and debug using oscilloscopes, probes, interposers, and software

Oscilloscope

Probes & Accessories

Interposers

Software

Resources

Technical Docs

Videos

Webinars

Manuals

Name
LPDDR5 Datasheet QualiPHY 2 (QPHY2-LPDDR5) datasheet outlines testing capabilities, ordering information and more for engineers interested in memory design.	Datasheet
DDR5 Datasheet Test all stages of design for DDR5 System Level (at the BGA). This Datasheet outlines tools made for early turn-on through QualiPHY automated compliance testing. Perform debugging and compliance style measurements outlined by the JEDEC. Read about required equipment and ordering information.	Datasheet
DDR4/LPDDR4/LPDDR4X Datasheet QualiPHY (QPHY-DDR4) Datasheet outlines testing capabilities, ordering information and more for engineers interested in memory design.	Datasheet
DDR3/DDR3L/LPDDR3 Datasheet QualiPHY (QPHY-DDR3) Datasheet outlines testing capabilities, ordering information and more for engineers interested in memory design.	Datasheet
DDR2 Datasheet QualiPHY (QPHY-DDR2) Datasheet outlines testing capabilities, ordering information and more for engineers interested in memory design.	Datasheet
LPDDR2 Datasheet QualiPHY (QPHY-LPDDR2) Datasheet outlines testing capabilities, ordering information and more for engineers interested in memory design.	Datasheet
DDR & LPDDR Debugging Toolkit Datasheet LPDDR and DDR Debug supported all stages of design for DDR 2/3/4/5 and LPDDR2/3/4/4X/5/5X and allows for deep troubleshooting.	Datasheet

DDR5 Memory Test and Read-Write Separation

LPDDR5 Test & Debug with the LPDDR5-TOOLKIT

LPDDR5 Electrical Compliance Test Overview – QPHY2-LPDDR5

How to Copy DDR Debug Toolkit Settings to QualiPHY 2

Become an Expert in DDR Memory Physical Layer Testing for DDR Debug, Compliance and Validation

Join Teledyne LeCroy for this masterclass webinar series to learn about the basics of DDR testing with oscilloscopes, including common test preparation and challenges, the difference between compliance and debug test tools, and practical tips and techniques to increase your DDR validation efficiency and apply the correct debug tools.

Part 1: Fundamentals of DDR Memory Testing

In this webinar, we'll be offering a comprehensive introduction to DDR interfaces along with the challenges encountered during testing. We will focus particularly on distinguishing between validation and compliance testing requirements, as well as preparing for DDR memory testing.

Part 2: Tips and Techniques for DDR Probing

In this webinar, we get specific on how to address real-world probing and connectivity issues that impact DDR measurement capabilities. We will provide examples of what to do or not do and a pre-compliance test checklist will be reviewed.

Part 3: DDR Debug and Virtual Probing

In this webinar, we provide practical advice on overcoming DDR test challenges using debug tools. Topics include real-world DDR debugging examples like logic, soldering, and power supply issues, DDR read/write separation, eye pattern formation, and addressing missing clock cycles. We'll also discuss DDR eye patterns, jitter in multiple scenarios, hardware-based read-write separation, and virtual probing techniques.

Part 4: What’s New with DDR5 Memory Testing

In this webinar, we will we provide details on how the JEDEC DDR5 and LPDDR5 specification and test requirements are different from previous versions of DDR, and how you can optimize your DDR5 and LPDDR5 memory testing.

Name
DDR4/LPDDR4/LPDDR4X Instruction Manual QualiPHY (QPHY-DDR4) Instruction Manual for step-by-step instruction on how to operate and test the DDR4, LPDDR4, LPDDR4X DRAM standards.	Product Manual
DDR3/DDR3L/LPDDR3 Instruction Manual QualiPHY (QPHY-DDR3) Instruction Manual for step-by-step instruction on how to operate and test the DDR3, DDR3L, LPDDR3 DRAM standards.	Product Manual
DDR & LPDDR Debugging Toolkit Instruction Manual DDR Debug supported all DDR 2/3/4/5 and LPDDR2/3/4/4X/5 and allows for troubleshooting tough problems. This manual helps you use the tool to it’s full potential	Product Manual
DDR2 Instruction Manual QualiPHY (QPHY-DDR2) Instruction Manual for step-by-step instruction on how to operate and test the DDR2 DRAM standard.	Product Manual
LPDDR2 Instruction Manual QualiPHY (QPHY-LPDDR2) Instruction Manual for step-by-step instruction on how to operate and test the LPDDR2 DRAM standard.	Product Manual
QPHY2-DDR5-SYS Instruction Manual QualiPHY 2 (QPHY2-DDR5-SYS) Instruction Manual for step-by-step instruction on how to operate and test the DDR5 standard.	Product Manual
QPHY2-LPDDR5 Instruction Manual QualiPHY 2 (QPHY2-LPDDR5) Instruction Manual for step-by-step instruction on how to operate and test the LPDDR5 standard.	Product Manual

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