Complete DDR4 test coverage as described by JESD79-4B
Support for all standard and custom speed grades
Separate bursts using DQ-DQS phase or DDR4 command bus
Statistically relevant results achieve measurement confidence
Report generation with pass/fail results and fully annotated worst case measurement screenshot
DDR Debug Toolkit integration for easy and flexible debug
- Maximize signal integrity with de-embedding and Virtual Probing
Accurate Burst Separation
Read and Write bursts can be separated based on DQ-DQS phase or based on the command bus when used in conjunction with the HDA125 High-speed Digital Analyzer. The HDA125 enables bursts to be separated using the commands sent from the controller, allowing for accurate burst separation even in situations with non-ideal signal integrity (e.g. reflections).
Due to the high level of variability in DDR measurements, it is important to make statistically relevant measurements to fully characterize DDR4 interfaces. By measuring thousands of cycles in one acquisition, the user can be more confident that they are catching the true maximum and minimum points for their measurement.
Most Flexible DDR4 Debug
QPHY-DDR4 uses the DDR Debug Toolkit to perform all compliance testing. Using the “Stop on Test” feature, the user can pause testing after each individual test and clearly see where the worst case measurement occurred. At that point the DDR Debug toolkit can be leveraged for further debug and upon completion, testing can be seamlessly resumed with one click of a button.
De-embedding and Virtual Probing
Teledyne LeCroy provides software tools which can be used to maximize signal integrity with DDR probing. The VirtualProbe package can virtually move the probe to the DRAM BGA, where it cannot be physical placed, and it will remove any effects of the probe or interposers through de-embedding. The VP@Rcvr (Virtual Probe at Receiver) math function can be used to model the circuit of the DIMM to reduce reflections.
DQ Input Receiver Compliance Mask
For the first time the DDR4 specification includes a compliance mask for the DQ input signal which replaces the traditional DQ setup and hold time measurements. QPHY-DDR4 automatically centers the mask in the DQ eye to test for any mask hits and reports the required shift from the DQS crossing to test tDQS2DQ. This eye diagram is also used to calculate the VIHL_AC peak to peak requirement.
The DDR4 specification requires clock jitter to be separated into random and deterministic components, which is a first for DDR specifications. QPHY-DDR4 leverages industry leading serial data algorithms to perform the jitter breakdown for tJIT(per). In addition to these tests, QPHY-DDR4 will test average clock period, absolute clock period, average high/low pulse width, absolute high/low pulse width, cycle-cycle jitter, duty cycle jitter, and cumulative error over n period tests.
tDQSQ verifies the skew between DQS and the associated DQ within a read burst. QPHY-DDR4 will perform this measurement on every DQ transition within a read burst. Upon completion each test will display a fully annotated "worst case measurement" screenshot which includes trace labels for the signals under test and relevant voltage levels.
SRI_diff, the DDR4 definition for input slew rate on DQS, measures the slew rate on every rising and falling edge within a write burst. QPHY-DDR4 will measure every transition within each write burst in the acquisition providing statistically meaningful results in a short period of time. In this case over 3,000 slew rate measurements were performed which ensures that the true maximum and minimum points have been caught without requiring multiple acquisitions.