PCI Express Analysis Solutions
LeCroy offers five PCI Express protocol analyzer platforms (Summit™ T3-16, Summit T3-8, Summit T28, Summit T2-16 and Edge T1-4). The Summit T3-16 Analyzer is LeCroy's fifth generation architecture and highest performance platform. It provides full bidirectional support of x16, x8, x4, x2, and x1 at data rates up to 8 GT/s. With 8 GB of trace memory, it offers enough capacity for analyzing and recording extensive PCI Express data streams. Supporting lane widths up to x8 at 8 GT/s, the Summit T3-8 offers the same powerful features and as an option allows for two T3-8 systems to be connected together to achieve a full x16 lanes at 8 GT/s. Ideal for embedded systems monitoring and analysis is the Summit T28, smaller and a more cost effective PCI Express protocol analyzer for x8 lanes at 5GT/s. The Summit T2-16 has similar features to the Summit T28 but supports a full x16 lanes. All Summit analyzer platforms use the PCI Express iPASS connector for probing. For portability and ease-of-use the Edge T1-4 Analyzer offers analysis support for x1-x4 lanes at 2.5GT/s with its topside PCIe connector built for Device Under Test(DUT). The Edge is LeCroy's most optimized and low cost analyzer for analysis of PCIe 1.1 add-in-boards.
LeCroy's PCI Express Protocol Analyzer solutions employ high impedance, non-intrusive probing technology thereby allowing fully unaltered data pass-through. In addition, it leverages the intuitive and powerful LeCroy Trace expert software system, embedding a deep understanding of the PCI Express protocol hierarchy and intricacies and presents this knowledge to the user in a colorful, intuitive and easy to use graphical display, allowing users to quickly capture and validate PCI Express product designs. These analyzers enable IP, semiconductor, switch, software and system developers as well as add-on card vendors to quickly identify protocol violations and ultimately reduce development and debugging time.
Developers can use LeCroy's PCI Express Protocol solutions to easily capture and decode PCI Express Transaction Layer Packets (TLPs), Data Link Layer Packets (DLLPs), and low-level link traffic, including Training Sequences and Skip Ordered-sets. Some of the errors detected include: 8b/10b errors, such as invalid symbols and incorrect running disparity; CRC errors; idle data errors; and EDB (End-of-Packet Bad) errors. They also provide a detailed display of split transactions, correlating requests transmitted from one PCI Express endpoint with completions received from the endpoint at the opposite end of the link.
LeCroy is well known for its technical leadership. Customers have come to depend on LeCroy supporting protocols while they are early in development when these tools are essential.
The PCI Express exercisers assist with generating PCI Express transactions, observing behavior, and performing both stress testing and compliance testing. The Summit Z3-16 supports the new Specification 3.0 ("Gen3") data rates of 8 GT/s across up to 16 lanes. The PETrainer ML Exerciser supports up to x4 lane widths at data rates of 2.5 GT/s. As complete solutions, both the Summit T3-16 and Summit Z3-16, or PETracer/Trainer™ systems give you the unique ability to record (capture) live traffic, modify the traffic, and then playback the exact data stream, or "script," using the exerciser.
Protocol Test Card
LeCroy offers an integrated and automated compliance testing system, including the Protocol Test Card, approved by the PCI-SIG® as a standard tool for compliance testing for developers working with the new Gen2 specification.
PCI Express Physical Layer Testing
The LeCroy SDA 6020 Analyzer and PCI Express Compliance and Development software offer a complete test and debug. QPHY-PCIe provides a highly automated solution for PCI Express 1.1.
The LeCroy SDA 13000 can perform PCI Express 2.0 Compliance Test and Debug. It can acquire and quickly analyze PCI Express 2.0 signals using the SigTest(PCI-SIG Compliance Utility). The SDA 13000 has the memory depth to acquire all required 1 million UI in a single acquisition. Waveforms can be saved in the TRC format and quickly analyzed by SigTest. Built into the standard SDA tools are the 14 Masks, 3 PLLs and 2 Jitter Filters specified by PCI-SIG.
Learn more about PCI Express Technology
PCI Express Overview
Peripheral Component Interconnect Express(PCIe) protocol was developed by Microsoft, Dell, IBM, Intel, and others in 2002. It was first called 3GIO but later became known as PCI Express. The PCI Express architecture is a state-of-the-art serial interconnect technology that keeps pace with recent advances in processor and memory subsystems. From its initial release at 0.8V, 2.5GT/s(Giga Transfers), to the newly announced Gen3 at 8GT/s the PCI Express technology roadmap will continue to evolve, while maintaining backward compatibility, well into the next decade with enhancements to its protocol, signaling, electromechanical and other specifications. The PCI Express architecture retains the PCI usage model and software interfaces for investment protection and smooth development migration. The technology is aimed at multiple market segments in the computing and communication industries, and supports chip-to-chip, board-to-board and adapter solutions at an equivalent or lower cost structure than existing PCI designs. PCI Express 2.0 currently runs at 5GT/s or 500MBps per lane in each direction, providing a total bandwidth of 16GBps in a 16-lane configuration which is the largest size in use.
PCI Express Gen3 will run at 8GT/s but will use a different encoding system to double the data rate but keep power consumption as low as possible.
Why PCI Express?
The PCI bus is aging. Continued emergence of faster CPU and memory speeds, high-performance graphics, gigabit networking and other applications requiring higher bandwidth have made this once proud I/O the bottleneck. PCI simply cannot keep up with these faster applications. In addition, today's internal systems are composed of numerous and sometimes proprietary interconnects, thus making it difficult for multiple internal and external systems to have a unified I/O.
PCI Express is ready to meet the challenges of new and emerging applications for the next decade. It is designed to tie together many different chip-level I/O components within PC systems and to partition the system by providing very high-speed interconnections between different functional units - which will enable radical new designs.
The PCI Express architecture is a general-purpose I/O interconnect that can scale across multiple market segments in both the computing and communications industries. It is designed to provide connectivity as a chip-to-chip interconnect, I/O interconnect for adapter cards, an I/O attach point to other interconnects such as 1394b, USB2.0, InfiniBand and Ethernet and as a graphics I/O attach point for increased graphics bandwidth.
The key features of PCI Express technology are:
- Scalable performance, achieved through wider link widths (x1, x2, x4, x8, x16, x32)
- Advanced power management
- Compatible with existing PCI OS's and software drivers
- Data integrity and error handling
- Support for real-time data traffic
- Support for multiple connection types such as chip-to-chip and board-to-board connectors
A PCI Express Link is composed of two low-voltage differential pairs; a dual simplex connection between A and B devices. Data transmission between A and B are run simultaneously in both directions. Links cannot be configured asymmetrically, with more lanes in one direction versus the other.
PCI Express Link
PCI Express is intended to support multiple connection types, including chip-to-chip connectors on a system board; board-to-board connectors such as PCI add-in card interconnects today; docking stations for mobile platforms; as well as new form factors yet to be developed. This flexibility will allow for innovative and radical designs in platforms for years to come.
Why use a Protocol Analyer for PCI Express?
Using a PCIE Protocol Analyzer from LeCroy allows developers to see PCIe transactions from the low level wire up through to the upper PCIe protocol layers. From this diagram a bit stream is extracted to a packet. Packets are extracted into one or more transactions. Transactions may be further integrated into higher level transfers. Looking at data this way allows better understanding of how well the protocol has been implemented and is performing.
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