Support
Technical Library

Technical Library

The Conference Proceedings section of the Teledyne LeCroy Technical Library lets you search for, browse, and print the latest technical documentation. A search aid allows you to filter documents by category or keyword.

Conference Proceedings on this site are available in PDF format for easy download.

Conference Proceedings

Search by Category: Search by Keyword(s):
 
Search Results: Your search found 30 matches. Page 1 of 3 pages.
Results 1-10

 

Practical Considerations in Measuring Power and Efficiency - APEC2016 Industry Session

Practical Considerations in Measuring Power and Efficiency on PWM and Distorted Waveforms during Dynamic Operating Conditions

DesignCon 2011 - Unified Methodology of 3D-EM/Channel Simulation/Robust Jitter Decomposition

Developing Unified Methods of 3D Electromagnetic Extraction, System Level Channel Modeling, and Robust Jitter Decomposition in Crosstalk Stressed 10Gbpsec Serial Data Systems

DesignCon 2014 - Jitter Noise Duality

We compare two approaches where the structure of the eye diagram is considered either as a timing uncertainty or alternatively a vertical uncertainty. We show that only the second view allows accurate BER evaluation, even if the eye is closed. It follows from BER definition that its proper evaluation should be based on considering the two portions of the eye diagram, and by their separate integration. With such understanding of BER, it turns out that the jitter-induced vertical noise can be considered same way as the signal’s ISI, although correlated with the latter.

Practical Techniques and Tips for Probing and De-Embedding

Getting a clean signal to your oscilloscope has become a complicated business. How much does probe loading matter? What is the effect of the probe's calibration? Are there reflections to worry about? If you're de-embedding, how do you separate de-embedding problems from signal problems? In this session, practical examples are used to show how these considerations affect high-speed measurements, and how to apply knowledge about the tools at hand to ensure the best results.

DesignCon 2014 - Have your cake and eat it, too: Engineering measurements at fabrication for channel design and process control

This paper demonstrates the acquisition of advanced circuit board performance parameters from breakaway test coupons measured right at the PCB fabricator. We show how to acquire S-parameter and TDR-based measurements up to 30 GHz using robust probes and test coupon fixtures. The measurements provide pass/fail tests for process control and they provide model parameters as feedback to improve channel design. By way of example, we demonstrate measurements of several representative test coupons, perform total loss tests, such as SET2DIL, and extract design parameters that can be used to improve EDA channel models.

DesignCon 2014 - Computation of Time Domain Impedance Profile from S-Parameters: Challenges and Methods

When computing time-domain impedance profile from measured S-parameters, we face two types of problems. First is caused by low quality of sampled S-parameters, such as insufficient resolution, band-limiting, noise etc. These limitations create certain numerical challenges, such as response aliasing, ringing and noncausality. The computed impedance becomes sensitive to termination conditions set up at the far end of the connector.

DesignCon 2014 - Essentials of Jitter Tutorial

Jitter - every engineer designing a serial data communications channel needs to understand its impact on their circuit. In this introductory level 3-hour tutorial, we will teach you the essential principles of jitter, from the timing measurements that are at the heart of jitter analysis to the Tj/Rj/Dj results derived from model-based extrapolations, and everything in between, including the essentials of data dependent, periodic and bounded-uncorrelated jitter and the world of jitter tracks, spectra, CDFs, etc.

Tuning DDR4 for Power and Performance

Presentation from MemCon 2013

DesignCon 2012 De-embedding in High Speed Design

A common problem encountered while measuring S-parameters of a device under test (DUT) is that it is relatively easy to calibrate a network analyzer to the end of coaxial test cables, but difficult to connect coaxial test ports directly to board-level DUTs.
123