SDA-FBDIMM

• Built for X-Replay™Automated Software – compatible with all LeCroy High-performance Real-time oscilloscopes
• Test and Validation for FB-DIMM configurations from 3.2 Gb/s to 4.8 Gb/s
• Test Suite conforms with JC-45 Validation and Verification Task Group specification – updated to Revision 0.85
• Built-in support for upcoming 4.8 Gb/s data rates and beyond
• Amplitude, Timing, Jitter, and Eye Measurements
• Custom Clock recovery supports Filtered Jitter measurements
• Supports all industry standard test fixtures

The SDA-FBDIMM compliance and analysis software solution for the SDA 11000 High-performance Serial Data Analyzer provides an extensive set of validation/verification and debug tools written in accordance with Joint Electron Device Engineering Council (JEDEC) AMB point-to-point electrical specification. Covered test functions include Transmitter, Receiver, and Reference Clock (RefClk) Tests.

In addition to standard eye pattern and jitter tests, the SDA-FBDIMM solution provides a complete set of amplitude and timing measurements, as defined in the JEDEC specification. This combination of measurements available in SDA-FBDIMM constitutes a truly automated test suite that meets the Fully Buffered DIMM (FBDIMM) requirements for point-to-point serial data links. The SDA-FBDIMM software takes advantage of all the advanced test and measurement tools available in LeCroy’s instruments:

• D11000PS High Bandwidth Probing System Available in dual-SMA input or Solder-In configurations give the user a choice between versatility and the highest signal integrity with the lowest probe loading across the entire bandwidth range.
• Jitter Wizard Tool Standard in the SDA 11000, ensures correct jitter measurement setup, with data, clock or a combination of data and clock signal inputs.
• Filtered Jitter measurements and Custom PLL configurations Allow users to understand the behavior of circuits by selectively applying custom PLL bandwidth and cutoff frequencies.
• Industry-leading, deep acquisition memory (Available up to 100 Mpts/Ch in 2 channel mode) enables true characterization of Spread Spectrum Clock (SSC) measurements required by FB-DIMM specification.

X-Replay user interface for FB-DIMM application

As hardware designers are quick to recognize, measurement results often need to be summarized and tabulated for quick specification verification. SDA-FBDIMM goes a step beyond by incorporating a unique application framework, where every experimental result is saved to a Open Database Connectivity (ODBC)-compatible database via the Export to XML utility. Sample applications that stand to benefit the most from the new software framework include, but are not limited to:

• Memory module developers who require comprehensive wafer/die characterization to define parametric performance and establish device performance capability.
• Device development teams working in parallel development cycles who need to combine, study, and interpret performance data and correlate test results with prior design runs.
• Manufacturing/Production test environments where key performance parameters are monitored, using control charts or other in-process indicators of device performance.

FB-DIMM Limits can be modifed to account for the effect of test fixtures

Ensuring backward-compatibility with legacy Double Data Rate (DDR) designs such as DDR-2 or DDR-3 requires the use of advanced probing tools. LeCroy provides connectivity to DDR test scenarios through LeCroy’s family of WaveLink active differential probes, all compatible with SDA 11000.
Similarly, the use of SDA-FBDIMM in conjunction with the deep memory and powerful analysis library of the SDA instrument family greatly simplifies the verification process.

Clock recovery circuitry and clock extraction via Phase-Locked Loops (PLLs) is another significant design consideration. The flexible numerical clock recovery options in the SDA allow for the simulation of virtually any real receiver PLL configuration thus allowing the simulation of “what if” scenarios. Jitter results can be measured exactly as the receiver would see them.

FB-DIMM RefClock Jitter

FBDIMM Measurements

As hardware designers are quick to recognize, measurement results often need to be summarized and tabulated for quick specification verification. These test results, together with instrument and signal acquisition/test condition setups, create a fully documented record. SDA-FBDIMM incorporates a choice of automatic HTML, PDF, or RTF report generation formats. The test reports contain tabulated numerical values for each individual test result including PASS/FAIL and specification limit columns.

FB-DIMM Limits can be modifed to account for the effect of test fixtures

While the SDA instrument family adds the ability to measure jitter and eye patterns in real time, the SDA-FBDIMM package leverages the Advanced Serial Data Analysis Library, which provides the most extensive choice of jitter measurement conditions for reference clock or data signals, and in accordance with JEDEC specification. The SDA provides pinpoint accuracy for eye mask violation locator, even in the presence of Spread Spectrum Clocking (SSC).

• FB-DIMM Parametric test fixture (Agilent N4236A or equivalent) for Transmitter tests
• FB-DIMM Slot test fixture (Agilent N4238A or equivalent) for Receiver tests
• Channel Test Card (CTC) fixture or Certified Motherboard for Reference Clock tests
• AMB Parametric Test Fixture (Ball Grid Array) Agilent N4235A or equivalent.

Test Number	Description
Reference Clock Tests
Reference Clock Frequency	Test 1.1
Single-ended Maximum and Minimum Clock Voltages	Tests 1.2, 1.3
Absolute Crossing Point	Test 1.4
Voltage Crossing Variation	Test 1.5
Rising and Falling Edge Rate Variation and Mismatch	Tests 1.6, 1.7, 1.8
Duty Cycle of Reference Clock	Test 1.9
Deterministic Jitter of Reference Clock	Test 1.10
Transmitter Tests
Differential Peak-to-Peak Output Voltage for Small Regular and Large Voltage Swing	Tests 2.1, 2.2, 2.3
DC Common Mode Output Voltage for Small and Large Voltage Swing	Tests 2.4, 2.5
De-emphasized Differential Output Voltage Ratio for –3.5 and –6 dB	Test 2.6
AC Peak-to-Peak Common Mode Output Voltage Ratio for Small, Regular and Large Voltage Swings	Tests 2.7, 2.8, 2.9
Maximum Single-ended Voltage in EI (Electrical Idle) Condition, DC+AC	Test 2.10
Maximum Single-ended voltage in EI (Electrical Idle) Condition, DC Only	Test 2.11
Maximum Peak-to-Peak Differential Voltage in EI Condition	Test 2.12
Single-ended Voltage in D+/D–	Test 2.13
Minimum TX Eye Width	Test 2.14
Maximum TX Deterministic Jitter (2.15) fbaud/10	Test 2.15
Instantaneous Pulse Width fbaud/10	Test 2.16
Differential TX Output Rise/Fall Time	Tests 2.17, 2.18
Mismatch between Rise/Fall Times	Test 2.19
Receiver Tests
Differential Peak-to-Peak Input Voltage	Test 3.1
Maximum Single-ended Voltage for EI Condition, DC+AC	Test 3.2
Maximum Peak-to-Peak Differential Voltage for EI Condition	Test 3.3
Single-ended Voltage on D+/D–	Test 3.4
Maximum Rx Inherent Deterministic Timing Error	Test 3.5
DC Common Mode of the Input Voltage	Test 3.6
AC Peak-to-Peak Common Mode of the Input Voltage	Test 3.7
Ratio of VRX-CM-ACp-p to Minimum VRX-DIFFp-p (3.8)	Test 3.8