DDR Debug Toolkit The DDR Debug Toolkit is designed to accelerate DDR design work in the early turn-on, validation and pre-compliance stages as users prepare for compliance testing. Integrated into the MAUI scope app, users can build out case by case scenarios with multiple analysis areas, perform decode and triggering on the Command Bus and dive into optimizing design stages with JEDEC specific eye diagrams, mask testing and DDR specific measurements.
QPHY-DDR4 Teledyne LeCroy’s QPHY-DDR4 automated compliance software enables engineers to consistently test DDR4 and LPDDR4/4X memory standards set by the JEDEC specification. This 4th generation of memory provides nearly double the transfer speeds of previous ranges and lower operating voltages. QualiPHY automated compliance software has a complete set of Clock, Electrical, and Timing tests outlined by the JEDEC. Paired with the DDR Debug Toolkit provides the tools to confidently test all stages of memory design, from initial turn-on through final compliance test