Teledyne LeCroy’s Summit™ T54 joins the Summit™ Family as the high performance protocol analyzer at PCIe 5.0 architecture. The new Summit™ T54 protocol analyzer based on the PCIe 5.0 specification supports up to 32GT/s and up to x4 lane width for protocol analysis. Companies that are interested in testing PCIe 5.0 based I/O cards such as Storage Controllers, Ethernet, Fibre Channel, Infiniband, and others will now be able to get all of the protocol analyzer debugging features they need, while being able to better manage their costs. SSD storage applications will also benefit from the integrated support for SSD bus protocols such as PCIe/ NVMe/ SMBus/ NVMe-MI/ TCG and others. When combined with Teledyne LeCroy’s Summit™ Z416 protocol exerciser, the Summit™ T54 will provide a deeper understanding of test results on a variety of test configurations. Teledyne LeCroy’s wide range of high speed interposers and probes provide full flexibility and connectivity to CEM and other form factor sockets on system boards as well as solder down and mid-bus probes.
PCIe 5.0 Technology
PCIe 5.0 technology achieves twice the effective data throughput rate of the PCIe 4.0 standard through a combination of increased data bit rate (16 GT/s moving to 32 GT/s), PCIe 5.0 uses the same encoding as PCIe 4.0 that has proven reliable for data transmission.
PCIe 5.0 Speeds
With advanced features such as support for PCI Express Spec 5.0, data rates of 2.5, 5, 8, 16, 32 GT/s, lane widths from x1 to x4, and a full 64 GB of trace memory, the Summit T54 Protocol Analyzer provides unmatched capability and flexibility for developers and users of advanced PCI Express products. The Summit T54 is by far the most advanced and sophisticated PCI Express Analyzer available in the market today.
As with other Teledyne LeCroy PCI Express analyzers, the Summit T54 leverages the intuitive and powerful CATC Trace analysis software system, embedding a deep understanding of the PCI Express protocol hierarchy and intricacies. The colorful, intuitive and easy to use graphical display allows you to quickly capture and validate PCI Express product designs. All Teledyne LeCroy PCI Express protocol analyzers employ high-impedance, non-intrusive probing technology, thereby allowing fully unaltered data pass-through.
In addition to a full suite of advanced hardware and software features, the Summit T54 provides user-convenience and analysis features, such as support for "lane swizzling" which allows a board developer to lay out a Mid-Bus probe pad with lanes in non-standard order, simplifying the design of the board. Internally the Summit T54 maps the lanes back into their correct order and accurately displays the embedded bus traffic. Other software features include enhanced error checking for automatic identification of additional error types, more compact trace files that allow for faster analysis of trace data, and the choice of simplified or advanced modes for setting up trace recording options.
The raw recording mode, Bit Tracer, allows bytes to be recorded as they come across the link, allowing debugging of PHY layer problems and combining the features of a logic analyzer format with a protocol analyzer format. The new auto sense link feature monitors negotiation between devices of different lane widths, and the bifurcated link support recombines multilink PCI Express operations that have been separated into narrower links.
The Summit T54 also supports Ethernet LAN port as a standard feature. By connecting over a LAN, engineers can operate the system remotely (e.g., install the client software on their desktop systems, and control an analyzer operating in a remote lab). Also, multiple engineers working collaboratively can time-share use of a single analyzer, reducing the need for an additional analyzer for each engineer, and increasing the cost effectiveness of the product.
Debug in any PCIe environment
By leveraging years of experience in protocol analysis tools for emerging markets, Teledyne LeCroy's PCI Express protocol analyzers blend sophisticated functionality with practical features to speed the development of PCI Express IP cores, semiconductors, storage, graphics, servers, workstations, bridges, and switches.