Sierra T244

• Performance - Parallel ATA does not have scalability to support several more speed doublings, and it is nearing its performance capacity. By contrast, Serial ATA defines a roadmap starting at 1.5 gigabits per second (equivalent to a data rate of 150 MB/s) up to 6Gigabits per second.
• Lower Voltage - Parallel ATA's 5-volt signaling requirement will be increasingly difficult to meet as the industry continues to reduce chip core voltages. Serial ATA is better aligned with future manufacturing processes. It reduces signaling voltages to approximately 250 millivolts (1/4 volt).
• Pin Count - Currently, the parallel ATA interface has 26 signal pins going into the interface chip. Serial ATA uses only 4 signal pins, improving the pin efficiency and accommodating a highly integrated chip implementation.
• Improved Cabling - Parallel ATA bulky ribbon cables contain 40-pin header connector. Serial ATA introduces thin, flexible cabling scheme that offers longer cables and improved airflow within the chassis.
• Software Compatible - Serial ATA is compatible at the register level with parallel ATA. This means Serial ATA requires no changes to existing software and operating systems in order to function, and it provides backward compatibility with existing operating environments.
• SAS Compatibility - A significant feature offered by Serial ATA is the expectation that SATA will be form-factor compatibility with Serial Attached SCSI. SATA drives will plug directly into Serial Attached SCSI connectors and if supported in the system, will transparently operate as a SATA device. This allows systems to be deployed that can use either Serial Attached SCSI drives, for their high performance or SATA drives that will provide a lower-cost-per-megabyte storage platform.
• SATA DevSleep™ - The latest SATA 3.2 specification includes DevSleep, a new feature designed to reduce power consumption and allow longer battery life as well as energy savings in the data center. It re-uses the 3.3V power pin on the SATA interface to instruct the device to enter the Sleep state where it uses less power than Slumber mode. With most low power modes, this new feature requires extensive testing at the protocol layer to ensure a seamless user experience.

• Serial ATA is a full duplex protocol. There is a continuous flow of signals from each device moving down the bus. The device and host are transmitting (TX) and receiving (RX) at the same time.
• Bidirectional traffic pattern eliminates the need for bus negotiation overhead
• Data characters vs Primitives - Primitives are the simplest elements within the Serial ATA protocol. Primitives are 32-bit DWORDs used to initiate control of the serial line functions (X_RDY, CONT, etc...). In addition to these "handshaking" and flow control signals, Primitives are also used to delimit or "frame" user data.
• Frame Information Structure (FIS) - A frame is an indivisible unit of information exchanged between a host and device. A frame consists of a SOF primitive, a Frame Information Structure (FIS), a CRC calculated over the contents of the FIS, and an EOF primitive. A FIS is the user payload of a frame; a frame is a group of Dwords that convey information between host and device as described previously.

• Serial ATA Working Group
• SearchStorage Serial ATA Technology
• T13 Technical Committee

Designed for the SAS 4.0 (24 Gb/s) standard, the Sierra T244 provides the most accurate capture, display and analysis of the next generation SAS protocol. Featuring the industry's highest-fidelity probe design, the Sierra T244 seamlessly locks on 24G signaling without distorting the dynamic link training sequence. For comprehensive testing and verification of components, backplanes and subsystems, the Sierra platform delivers true end-to-end visibility to help ensure SAS 4.0 performance and reliability.

The Sierra T244 features custom probe technology known as T.A.P.4™ (Transparent Acquisition Probing) which has been field-proven in Teledyne LeCroy's 32Gb/s Fibre Channel and PCIe 4.0 analyzer platforms. Leveraging this cutting-edge analog front-end, the T244 provides a robust analysis platform well suited for both silicon bring-up, as well as multi-vendor interoperability testing. The T.A.P.4 probe design sets the standard for accuracy by seamlessly capturing and analyzing the critical link initialization and speed negotiation sequence. Designed to operate transparently, the Sierra passes signals that are nearly identical to the original DUT signaling. This ensures the system-under-test behaves consistently while the Sierra records the 24 Gb/s link training coefficients without distorting the dynamic equalization process.

The Sierra chassis supports a convenient design for stacking or racking multiple units and still provide access to all data and control ports. Suitable for either bench-top or storage rack environments, the Sierra includes support for both USB 3.0 and Gigabit Ethernet host connections. Combining SuperSpeed upload with the convenience of USB plug-and-play connectivity can save hours of time over the life of the equipment. With the Ethernet port, the Sierra is fully addressable over the network with built-in utilities that display the current user, the IP Address and status. LEDs provide information on negotiated link speed, protocol error detection, link state, and whether OOB or data traffic is active. Memory configurations - from 32GB to 128GB -can address long recording times. A built-in port provides DC power for target devices to conveniently supply SSDs or HDDs with 12v or 5v power. The rear chassis also provides a sync-port capable of synchronizing trace captures from multiple analyzers.

Seamlessly integrated with Teledyne LeCroy's expert analysis software, the Sierra platform overcomes the struggles of legacy debug tools with a revamped graphical interface featuring easy to understand displays of protocol traffic. For viewing commands and frames in sequential order, the Spreadsheet View provides a traditional table format that can be customized to add any field in a separate column. The exchange level assembles frames and primitives into the logical SCSI command, data, and status transactions. This is critical for wide-port analysis where large gaps can occur between command and status. Full decoding of SMP Discovery request/response transactions makes it easy to troubleshoot scale-out storage applications.

Use the Frame Inspector to view primitives or drill-down on the 150-bit SPL packet structures including headers, payloads, scrambled and unscrambled symbols. The field view provides unprecedented decoding of higher layer protocol fields, including the full CDB as well as SCSI sense data and ASC qualifiers to streamline troubleshooting. All of the expert analysis views can be used simultaneously and are automatically synchronized / displayed within one application. Any combination of display and filter options can be configured as the default view making it faster to interpret captured traffic.

The Sierra provides hardware triggering to pinpoint protocol events of interest. Trigger events can be specified at the lowest levels including error conditions, bus states, primitives (, etc...) header fields (packet type, LBA, etc...), or SCSI parameters (CDB, Tag, etc...). The Advanced mode offers 24 sequential states, 4 independent timers, multiple counters, the ability to pre-filter at each state, and the ability to assign individual triggers to each port pair. Users can define sophisticated sequential event trigger scenarios including more complex events such as timing violations between state changes. From speed negotiation to protocol errors, virtually any logical SAS or SATA event can be defined as the trigger event.

The Sierra SAS verification system provides extensive traffic metrics and statistics to help locate and identify protocol issues. Traffic Summary reports are hyperlinked to the actual trace events. Navigation in the spreadsheet view is easy with Quick-Find. Click on any field and Quick-Find populates the search window with the highlighted string allowing easy navigation forward or backward. Add Boolean operators to find lower or higher values. The Quick Filter uses the same easy mechanism to hide redundant fields. Markers can be added, searched and displayed as tooltips.

With best-in-class features including T.A.P.4™ probing, 128GB recording memory, and SuperSpeed 3.0 data upload ports, the Sierra T244 system helps reduce time-to-market for storage developers.