PCIe NVMe CXL
The Summit Z516 Exerciser is Teledyne LeCroy's latest generation PCI Express (PCIe) protocol exerciser and first Compute Express Link Exercsier, leveraging many years of experience in providing advanced protocol test tools to the PCI Express community. Supporting traffic generation at data rates to 32 GT/s with link widths up to 16 lanes, the system is designed for developers who need a protocol test system supporting the PCI Express 5.0 specification.
The Summit Z516 supports full traffic generation and device/host emulation, as well as providing the industry a platform for development of standardized compliance test suites. In addition the system provides error injection functions to enable developers to test error recovery routines important to reliable interoperability of PCI Express 5.0 and CXL products.
Wealth of PCI Express Features
Intuitive software controls blend sophisticated traffic generation when used with an external Summit series analyzer with ease-of-use, allowing test suites to be rapidly customized to meet specific test requirements. One feature that helps troubleshoot PCIe-based links is the ability to fully exercise the Link Training & Status State Machine (LTSSM) transitions. Powerful scripting language also allows for the creation of Transaction Layer Packets (TLPs) and Data Link Layer Packets (DLLPs) at PCIe 5.0 data rates of 32.0 GT/s. Flow Control and ACK/NAK's policies and structures can be defined and generated under user control.
Features addressing LTSSM structures include providing bus traffic to emulate all the states of the LTSSM from the Detect state, to the L0 state and maintaining the L0 state between the host and device. The exerciser also supports lane reversal and can control all polarity and scrambling configurations. An important feature to note is that traffic emulation supports dynamic equalization in addition to skipping the EQ phases entirely. The exerciser also has the capability to perform error injection for training sequences, as well as Data Link and Transaction Layer traffic, both at the packet level and on a per lane basis.
Packet fields not explicitly specified by the user are generated automatically (such as packet numbering and CRCs). The configuration space can be emulated for any device including endpoints, bridges and switches. Support for all PCIe 5.0 data rates allows the Summit Z516 to produce test cases that test the device's ability to auto-negotiate data rates with other devices.
In addition, the ability of the Summit Z516 to produce a wide variety of programmed traffic allows the user to introduce controlled error conditions. As an example, a trace file captured by the external Summit series PCIe protocol analyzer can be exported and used as the basis for a test script, with selected programmed errors introduced at critical stages to test the device's ability to recognize and recover from error conditions. This allows for detailed testing of simple error recovery and complex multiple error conditions, creating more resilient products that perform well even under less than ideal conditions.
Full CXL Traffic Generation and Error Insertion Capabilities
Compute Express Link (CXL) is a new high-speed CPU-to-Device and CPU-to-Memory interconnect designed to accelerate next-generation data center performance. CXL is based on the PCI Express 5.0 Physical layer with speeds up to 32.0 GT/s. The exerciser scripting language also allows for the creation of CXL Transaction Layer Packets (CXL.io TLPs) and Data Link Layer Packets (CXL.io DLLPs) in addition to CXL.mem and CXL.cache requests at PCIe 5.0 data rates of 32.0 GT/s. Flow Control and acknowledge policies and Flit structures for each of the CXL protocols: CXL.io, CXL.mem, CXL.cache can be defined and generated under user control.
Summit Z516 can also generate CXL.io, CXL.cache, and CXL.mem packets that can be dynamically multiplexed on the link. It can provide traffic and error generation for systems through all layers from the FlexBus Physical layer and Flits all the way up to the Link and Transaction Layers.
Test Platform
PXP-500 Test Platform provides Host Emulation Teledyne LeCroy's PCIe 5.0 Test Platform for the Summit Z516 Exerciser provides a convenient, powerful and flexible two CEM compliant backplane for PCIe devices at data rates up to 32 GT/s and with lane widths up to x16. The Test Platform allows the Summit Z516 to act as a host system, enabling extensive protocol-level testing of PCIe devices. For use as a host emulator, the Summit Z516 is plugged into one of the PCIe x16 slots and connected to the power source, then the Device Under Test (DUT) is plugged into the alternate PCIe x16 slot with slot power provided to the DUT by the Test Platform. The Test Platform comes with 2 test Buses CEM to CEM connector and CEM to SFF-TA-1002 connector. Only one bus can be used at a time with the Summit Z516. In addition to using the Test Platform with the Teledyne LeCroy Summit Z516, the user can connect two of their own devices and use the Test Platform as a PCIe backplane.