Physical Layer Test Solutions

Physical Layer Test Solutions

Tools tailored towards embedded computing speed up test and debug.

  • Support for widely adopted inter-chip communication standards
  • Comprehensive DDR solutions
  • TDME options for faster debug and validation efficiency
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Testing and Training

Teledyne LeCroy’s Austin Labs is a leading provider of independent testing and training services focused on server, storage, and networking interfaces, including PHY testing and protocols analysis.

  • Complete Ethernet Network and Fibre Channel Fabric on site or virtual training classes
  • Extensive hardware, integration/interoperation, failure analysis, and characterization test services
Explore Austin Labs

I2C, SPI, UART-RS232, USB 2.0 HSIC, 10/100/1000Base-T

Tools tailored towards embedded computing speed up test and debug.

I2C

I2C

  • Set ACK condition in all frame triggers
  • EEPROM read/write 2048-byte capability
  • Frame Length trigger capability
Explore I2C
SPI

SPI

  • Universal SPI support (no CS required)
  • Frame definition for USART protocols
  • Flexible Bits/Word Decode Setup
Explore SPI
UART-RS232

UART-RS232

  • Configurable byte structure
  • Customizable Message Frame for proprietary protocols
  • Supports 9-bit address
Explore UART-RS232
USB 2.0 HSIC

USB 2.0 HSIC

  • 480 Mbps USB2-HSIC decode capable
  • ProtoSync shows HSIC traffic at transaction level
  • Quick search for specific messages
Explore USB2-HSIC
10/100/1000Base-T

10/100/1000Base-T

  • Decode 10/100Base-T and MDIO
  • 10/100/1000Base-T Compliance Testing
  • Perform compliance tests without a probe
Explore 10/100/1000Base-T

Comprehensive DDR Solutions

The most comprehensive mixed signal oscilloscope solution for DDR2/3/4/5 and LPDDR2/3/4/5 physical layer testing.

DDR Toolkit

DDR Toolkit

  • Effortless Burst Separation
  • Eye Diagram Analysis
  • DDR-Specific Parameters
Physical Layer Compliance

Physical Layer Compliance

  • Complete JEDEC Test Coverage
  • Fully Annotated Screenshots
  • Automatic Report Generation
Unmatched Probing Versatility

Unmatched Probing Versatility

  • Robust solder-In tips
  • Superior signal fidelity
  • Simple and cost-effective

Trigger, Decode, Measure/Graph, Eye Diagram

Powerful and unique TDME options for faster debug and validation efficiency.

Highest Performance Triggers

Powerful Triggers and Decoders

  • Flexible Trigger Capability
  • Intuitive, Color-Coded Overlays
  • Filter decoder table on specific data
Explore Highest Performance Triggers
Measure and Graph Tools for Validation Efficiency

Unique Measure and Graph Tools

  • Serial Data DAC and Graphing Tools
  • Automated Timing Measurements
  • Bus Status Measurements
Explore Measure and Graph Tools for Validation Efficiency
Eye Diagrams & Physical Layer Testing

Flexible Eye Diagram Capability

  • 4 Simultaneous eyes
  • User-defined or pre-defined Masks
  • Additional Physical Layer Testing
Explore Eye Diagrams & Physical Layer Testing

Videos

TDME
Video

Technical Documents

Advanced Concepts for Characterizing and Troubleshooting Low Speed Serial Data Devices

Learn about various diagnostics that can be used for systems which incorporate various embedded computing standards.

Capture, Decode and Debug of Low Speed Serial Buses

An overview of methods to capture, view, decode, and debug a variety of low speed serial data protocols.

i2C Conditional Data Triggering

Learn how to isolate and identify specific I2C bus events to improve validation efficiency.

i2C Sub-Addressing Trigger Made Easy

Learn how to identify address spaces used internally by devices, quickly isolate, and improve validation efficiency.

Triggering on I2C Frames with no Data - An Example in I2C Data Length Triggering

Are you looking to focus special bus events? Do you have frames that contain no data at all? Learn how to isolate these and more.

Jitter Effects on 100BASE-T Timing

Jitter causes major problems in communications systems. Learn how to take a closer look at phase/time interval jitter to reveal major difficulties.

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