The Summit Z416 exerciser is Teledyne LeCroy's fifth generation PCI Express (PCIe) protocol exerciser, leveraging years of experience in providing advanced protocol test tools to the PCI Express community. Supporting traffic generation at data rates to 16 GT/s with link widths up to 16 lanes, the system is designed for developers who need a protocol test system supporting the PCI Express 4.0 specification.
In addition to traffic generation, the system also supports protocol analysis capability, featuring the industry-standard CATC Trace as well as a wide variety of other traffic displays and data reports. The Summit Z416 supports full traffic generation and device/host emulation, as well as providing the industry a platform for development of standardized compliance test suites. In addition the system provides error injection functions to enable developers to test error recovery routines important to reliable interoperability of PCI Express 4.0 products.
A Wealth of Features
Intuitive software controls blend sophisticated traffic generation and analysis capability with ease-of-use, allowing test suites to be rapidly customized to meet specific test requirements. One feature that helps troubleshoot PCIe links is the ability to fully exercise the Link Training & Status State Machine (LTSSM) transitions. The powerful scripting language also allows for the creation of Transaction Layer Packets (TLPs) and Data Link Layer Packets (DLLPs) at PCIe 4.0 data rates of 16 GT/s. Flow Control and ACK/NAK's policies and structures can be defined and generated under user control. Features addressing LTSSM structures include providing bus traffic to emulate the all states of the LTSSM from the Detect state, to the L0 state and maintaining the L0 state between the host and device. The exerciser also supports lane reversal and can control all polarity and scrambling configurations. An important feature to note is that traffic emulation supports dynamic equalization and Skip EQ training and can handle autonomous speed switching between all combinations of speeds. The exerciser also has the capability to perform error injection for training sequences, as well as standard traffic, both at the packet level and on a per lane basis. Packet fields not explicitly specified by the user are generated automatically (such as packet numbering and CRCs). The configuration space can be emulated for any device including endpoints, bridges and switches. Support for all PCIe 4.0 data rates allows the Summit Z416 to produce test cases that test the device's ability to auto-negotiate data rates with other devices. In addition, the ability of the Summit Z416 to produce a wide variety of programmed traffic allows the user to introduce controlled error conditions. As an example, a trace file captured in the Analyzer can be exported and used as the basis for a test script, with selected programmed errors, introduced at critical stages to test the device's ability to recognize an recover from error conditions. This allows for detailed testing of simple error recovery and complex multiple error conditions, creating more resilient products that perform well even under less than ideal conditions.
Protocol Analysis Included
The Summit Z416 can also support up to sixteen (16) lanes of protocol analysis. Using its high speed trace memory (up to 8 GB), the Summit Z416 can monitor, capture, decode and analyze PCIe protocols with data rates up to 16GT/s (Gen4). The application display is highly configurable and can be modified to most users' debugging styles. Many features are available including a hierarchical display, protocol traffic summaries, detailed error reports, timing calculators, bus utilization graphs, and the ability to create userdefined test reports allowing developers to troubleshoot intricate problems and finish their projects on time. PCIe storage decodes such as NVMe, SATA Express (AHCI and ATA), SCSI Express (PQI and SOP), TCG (Trusted Computing Group), Precision Time Management (PTM) and virtualization decode such as Single and Multi-Root I/O Virtualization (SRIOV and MRIOV) as well as Address Translation Services (ATS) are available to broaden its capabilities to many different industry segments.
PXP-400 Test Platform provides Host Emulation Teledyne LeCroy's PCIe 4.0 Test Platform for the Summit Z416 Protocol Exerciser provides a convenient, powerful and flexible two CEM compliant backplane for PCIe devices at data rates up to 16 GT/s and with lane widths up to x16. The Test Platform allows the Summit Z416 to act as a host system, enabling extensive protocol-level esting of PCIe devices. For use as a host emulator, the Summit Z416 is plugged into one of the PCIe x16 slots and connected to the power source, then the Device Under Test (DUT) is plugged into the alternate PCIe x16 slot with slot power provided to the DUT by the Test Platform. In addition to using the Test Platform with the Teledyne LeCroy Summit Z416, the user can connect two of their own devices and use the Test Platform as a PCIe backplane.
Two test fixtures are also available to help with testing PCIe 4.0 devices: a PCIe Verification Load Board (VLB) for testing PCIe platforms such as server or mother boards, and the PCIe Validation Base Board (VBB) for testing PCIe Add-in Cards. Each of these test fixtures will aid developers in conducting electrical tests.
|Script Level Traffic Generation||Programmability to test PCI Express components with more precision and control|
|Convert Trace files into generation scripts||Recreate failure scenarios by replaying recorded traffic|
|Manual Error Injection||Verify fault handling and identify error recovery|
|Host/End-Point Emulation Support||End-point emulation (and optional host emulation) allow for designed stress and pre-testing of end-point and host devices for product verification|
|Programmable Data Link Layer||Ability to modify flow control, ACK/NAK, and retry behaviors|
|Flexible/programmable Transaction Layer||User ability to define arbitrary sequence of transactions, payload generation, and conditional repeat of transactions provide users with maximum flexibility|
|Programmable reply timers||Allows testing of ACK latency timeouts and retry mechanisms|
|In-band command/programmability||Allows control of testing from host system|
|Point and Click Script Editor||Complex scripts can be created quickly and easily|
|Programmable Configuration space||Test user defined endpoints|
|Link Training & Status State Machine (LTSSM) Testing||Exercise LTSSM state transitions for verification|
|Supports existing PCIe Protocol Suite API||Preserve investment in API Programs|
|Protocol Record, Decode and Analysis||One tool does both PCIe 4.0 traffic generation and protocol analysis|